A comparator-based switched-capacitor pipelined analog-to-digital converter

A new comparator-based switched-capacitor(CBSC) technique is proposed that eliminates the need for high gain op-amps in switched-capacitor circuits. The CBSC technique replaces the op-amp in switched-capacitor circuits with a comparator and a current source. Compared to op-amps, comparators suffer less from the negative effects of scaled CMOS. The technique is applicable to a broad class of sampled-data circuits including analog-to-digital converters, digital-to-analog converters, sample-and-holds, integrators and filters. As a proof of concept the technique is demonstrated in the design of a pipelined analog-to-digital converter. The prototype CBSC 1.5 b/stage pipelined ADC implemented in a 0.18 [mu]m CMOS process operates at 7.9MHz, achieves 8.6 effective bits of accuracy, and consumes 2.5mW of power. Sources of offset and nonlinearity are identified and analyzed. The analysis reveals the potential of the CBSC technique for lower power dissipation and provides design guidelines for energy efficient comparator-based switched-capacitor circuit design.

Department dc:contributor.department

Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2007

Author dc:creator

• Fiorenza, John Kenneth, 1977-

Advisor dc:contributor.advisor

• Hae-Seung Lee and Charles G. Sodini.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/40312

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/40312