{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/38590"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/38590","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"Intrachip clock signal distribution via si-based optical interconnect","abstract":"The Optical clocking has emerged as an innovative alternative approach to the electrical clocking, in order to overcome the difficulties associated with electrical interconnects in the synchronization of high-performance multi-GHz microprocessors. Because the on-chip optical interconnect must be embedded in current Si microprocessors, the optical clocking requires that the electronic-photonic integrated circuits (EPIC) consisting of Si-based photonic devices be developed on Si CMOS platform. We have identified the H-tree waveguide network and waveguide-integrated photodetectors as key photonic devices required for intrachip optical clocking for microprocessors. We have demonstrated successful optical signal distribution through SiON, waveguide H-tree network with 64 fanouts. A variable bending radius approach in H-tree design was used to optimize the performance of the optical clock signal distribution. The conventional y-splitter showed significant optical loss and unequal power-splitting ratio, which becomes increasingly problematic as the number of levels of a H-tree network increases and can result in increased skew. We devised a novel extended offset splitter, which reduced the splitting loss to < 3% and demonstrated 49:51 power split ratio. We have fabricated Si vertical p-i-n photodetectors that are monolithically integrated with compact silicon-oxynitride channel waveguides.","abstract_html":"The Optical clocking has emerged as an innovative alternative approach to the electrical clocking, in order to overcome the difficulties associated with electrical interconnects in the synchronization of high-performance multi-GHz microprocessors. Because the on-chip optical interconnect must be embedded in current Si microprocessors, the optical clocking requires that the electronic-photonic integrated circuits (EPIC) consisting of Si-based photonic devices be developed on Si CMOS platform. We have identified the H-tree waveguide network and waveguide-integrated photodetectors as key photonic devices required for intrachip optical clocking for microprocessors. We have demonstrated successful optical signal distribution through SiON, waveguide H-tree network with 64 fanouts. A variable bending radius approach in H-tree design was used to optimize the performance of the optical clock signal distribution. The conventional y-splitter showed significant optical loss and unequal power-splitting ratio, which becomes increasingly problematic as the number of levels of a H-tree network increases and can result in increased skew. We devised a novel extended offset splitter, which reduced the splitting loss to &lt; 3% and demonstrated 49:51 power split ratio. We have fabricated Si vertical p-i-n photodetectors that are monolithically integrated with compact silicon-oxynitride channel waveguides.","abstract_has_math":false,"creators":["Ahn, Donghwan"],"institution":"Massachusetts Institute of Technology","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Dept. of Materials Science and Engineering.","school":null,"contributors":[],"advisors":["Lionel C. Kimerling."],"committee_chairs":[],"committee_members":[],"year":2007,"date_issued":"2007","date_published":"2007","updated_at":"2026-07-22T22:22:19Z","subjects":["Materials Science and Engineering."],"languages":["eng"],"rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"rights_urls":["http://dspace.mit.edu/handle/1721.1/7582"],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/1721.1/38590","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Lionel C. Kimerling."]},{"key":"dc:contributor.department","label":"Department","values":["Massachusetts Institute of Technology. Dept. of Materials Science and Engineering."]},{"key":"dc:contributor.other","label":"Dc Contributor Other","values":["Massachusetts Institute of Technology. Dept. of Materials Science and Engineering."]},{"key":"dc:creator","label":"Author","values":["Ahn, Donghwan"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2007-08-29T20:31:57Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2007-08-29T20:31:57Z"]},{"key":"dc:date.issued","label":"Date","values":["2007"]},{"key":"dc:publisher","label":"Institution","values":["Massachusetts Institute of Technology"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Materials Science and Engineering."]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://dspace.mit.edu/handle/1721.1/7582"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/1721.1/38590"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2007.","Includes bibliographical references (leaves 171-182)."]},{"key":"dc:description.abstract","label":"Abstract","values":["The Optical clocking has emerged as an innovative alternative approach to the electrical clocking, in order to overcome the difficulties associated with electrical interconnects in the synchronization of high-performance multi-GHz microprocessors. Because the on-chip optical interconnect must be embedded in current Si microprocessors, the optical clocking requires that the electronic-photonic integrated circuits (EPIC) consisting of Si-based photonic devices be developed on Si CMOS platform. We have identified the H-tree waveguide network and waveguide-integrated photodetectors as key photonic devices required for intrachip optical clocking for microprocessors. We have demonstrated successful optical signal distribution through SiON, waveguide H-tree network with 64 fanouts. A variable bending radius approach in H-tree design was used to optimize the performance of the optical clock signal distribution. The conventional y-splitter showed significant optical loss and unequal power-splitting ratio, which becomes increasingly problematic as the number of levels of a H-tree network increases and can result in increased skew. We devised a novel extended offset splitter, which reduced the splitting loss to < 3% and demonstrated 49:51 power split ratio. We have fabricated Si vertical p-i-n photodetectors that are monolithically integrated with compact silicon-oxynitride channel waveguides.","(cont.) 830nm light guided by the waveguide was coupled to the photodetector through evanescent-wave coupling. We measured over 90% coupling efficiency. A two-step process that consists of 1) mode-coupling from a guided mode in the input waveguide to a leaky mode in the waveguide in contact with photodetector and 2) gradual evanescent wave coupling from waveguide towards photodetector, was a main coupling mechanism in the case of coupling with lower index-contrast waveguide, in contrast to high index-contrast waveguide case where coupling occurred nearly instantly at the front part of photodetector. It was shown that intentional introduction of an abrupt step in the waveguide at the transition interface to coupling region can improve mode-matching efficiency. It is beneficial to design photodetectors made of a thin absorbing layer from SOI or GOI(Germanium On Insulator) structures, in order to achieve the high speed and optical isolation. We studied the evanescent wave coupling behavior between silicon oxynitride (SiON) waveguides and thin Si photodetectors on SOI substrate at 850nm wavelength. We developed a simple and intuitive Leaky-Mode model using a ray-optics approach to determine the conditions for efficient coupling both in 2D and 3D structures.","(cont.) It is shown that the presence of leaky modes that are phase-matched between the waveguide and the Si layer is the key condition for efficient coupling. The study showed that the Si layer thickness is the most critical factor that needs precise design and process control in this structure. With higher An (=ncore - ncladding) waveguide design, the coupling rate to the Si layer is enhanced and becomes less sensitive to the Si layer thickness. Therefore, the change in coupling rate as a function of the Si layer thickness shows a sharp resonance-like dependence with low An waveguide design and a more muted oscillation-like dependence with high An waveguide. Although Ge photodetectors have received great attention recently due to their absorption capability at longer wavelengths such as 1550nm and the compatibility with Si CMOS, the development of waveguide-integrated Ge photodetectors have remained an imperative but unaccomplished task. We developed Ge photodetectors monolithically integrated with silicon oxynitride and silicon nitride waveguides deposited on top of the photodetectors. High efficiency (- 1.08A/W) and high-speed ( > 12 Gbit/s) performances were obtained.","(cont.) The Si CMOS-compatible detector devices retain their high performances even at low operation voltages, thus satisfying the low-voltage requirement of CMOS circuits, and have leakage currents that are low enough to meet the requirement of high-speed receiver designs. We also fabricated Ge photodetectors integrated with Si waveguides on SOI substrate. After the Si waveguide was formed on SOI substrate, Ge was selectively grown on a p+ doped area of Si waveguide and then a vertical p-i-n photodetector was formed by a n+ poly silicon. We have demonstrated the responsivity of 0.227 A/W and the 3dB frequency of 1.3 GHz. Based on the understandings on waveguide-to-photodetector coupling obtained from experimental and theoretical studies, we present an evanescent coupling design map for Si photonics materials. Some novel designs of integrated photodetectors are presented. Potential prototype structures for intrachip optical clock signal distribution system are discussed."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["Ph.D."]},{"key":"dc:title","label":"Title","values":["Intrachip clock signal distribution via si-based optical interconnect"]}]}],"canonical_facts":{"dc:contributor.advisor":["Lionel C. Kimerling."],"dc:contributor.department":["Massachusetts Institute of Technology. Dept. of Materials Science and Engineering."],"dc:contributor.other":["Massachusetts Institute of Technology. Dept. of Materials Science and Engineering."],"dc:creator":["Ahn, Donghwan"],"dc:date.accessioned":["2007-08-29T20:31:57Z"],"dc:date.available":["2007-08-29T20:31:57Z"],"dc:date.issued":["2007"],"dc:description":["Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2007.","Includes bibliographical references (leaves 171-182)."],"dc:description.abstract":["The Optical clocking has emerged as an innovative alternative approach to the electrical clocking, in order to overcome the difficulties associated with electrical interconnects in the synchronization of high-performance multi-GHz microprocessors. Because the on-chip optical interconnect must be embedded in current Si microprocessors, the optical clocking requires that the electronic-photonic integrated circuits (EPIC) consisting of Si-based photonic devices be developed on Si CMOS platform. We have identified the H-tree waveguide network and waveguide-integrated photodetectors as key photonic devices required for intrachip optical clocking for microprocessors. We have demonstrated successful optical signal distribution through SiON, waveguide H-tree network with 64 fanouts. A variable bending radius approach in H-tree design was used to optimize the performance of the optical clock signal distribution. The conventional y-splitter showed significant optical loss and unequal power-splitting ratio, which becomes increasingly problematic as the number of levels of a H-tree network increases and can result in increased skew. We devised a novel extended offset splitter, which reduced the splitting loss to < 3% and demonstrated 49:51 power split ratio. We have fabricated Si vertical p-i-n photodetectors that are monolithically integrated with compact silicon-oxynitride channel waveguides.","(cont.) 830nm light guided by the waveguide was coupled to the photodetector through evanescent-wave coupling. We measured over 90% coupling efficiency. A two-step process that consists of 1) mode-coupling from a guided mode in the input waveguide to a leaky mode in the waveguide in contact with photodetector and 2) gradual evanescent wave coupling from waveguide towards photodetector, was a main coupling mechanism in the case of coupling with lower index-contrast waveguide, in contrast to high index-contrast waveguide case where coupling occurred nearly instantly at the front part of photodetector. It was shown that intentional introduction of an abrupt step in the waveguide at the transition interface to coupling region can improve mode-matching efficiency. It is beneficial to design photodetectors made of a thin absorbing layer from SOI or GOI(Germanium On Insulator) structures, in order to achieve the high speed and optical isolation. We studied the evanescent wave coupling behavior between silicon oxynitride (SiON) waveguides and thin Si photodetectors on SOI substrate at 850nm wavelength. We developed a simple and intuitive Leaky-Mode model using a ray-optics approach to determine the conditions for efficient coupling both in 2D and 3D structures.","(cont.) It is shown that the presence of leaky modes that are phase-matched between the waveguide and the Si layer is the key condition for efficient coupling. The study showed that the Si layer thickness is the most critical factor that needs precise design and process control in this structure. With higher An (=ncore - ncladding) waveguide design, the coupling rate to the Si layer is enhanced and becomes less sensitive to the Si layer thickness. Therefore, the change in coupling rate as a function of the Si layer thickness shows a sharp resonance-like dependence with low An waveguide design and a more muted oscillation-like dependence with high An waveguide. Although Ge photodetectors have received great attention recently due to their absorption capability at longer wavelengths such as 1550nm and the compatibility with Si CMOS, the development of waveguide-integrated Ge photodetectors have remained an imperative but unaccomplished task. We developed Ge photodetectors monolithically integrated with silicon oxynitride and silicon nitride waveguides deposited on top of the photodetectors. High efficiency (- 1.08A/W) and high-speed ( > 12 Gbit/s) performances were obtained.","(cont.) The Si CMOS-compatible detector devices retain their high performances even at low operation voltages, thus satisfying the low-voltage requirement of CMOS circuits, and have leakage currents that are low enough to meet the requirement of high-speed receiver designs. We also fabricated Ge photodetectors integrated with Si waveguides on SOI substrate. After the Si waveguide was formed on SOI substrate, Ge was selectively grown on a p+ doped area of Si waveguide and then a vertical p-i-n photodetector was formed by a n+ poly silicon. We have demonstrated the responsivity of 0.227 A/W and the 3dB frequency of 1.3 GHz. Based on the understandings on waveguide-to-photodetector coupling obtained from experimental and theoretical studies, we present an evanescent coupling design map for Si photonics materials. Some novel designs of integrated photodetectors are presented. Potential prototype structures for intrachip optical clock signal distribution system are discussed."],"dc:description.degree":["Ph.D."],"dc:identifier.uri":["http://hdl.handle.net/1721.1/38590"],"dc:language.iso":["eng"],"dc:publisher":["Massachusetts Institute of Technology"],"dc:rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"dc:rights.uri":["http://dspace.mit.edu/handle/1721.1/7582"],"dc:subject":["Materials Science and Engineering."],"dc:title":["Intrachip clock signal distribution via si-based optical interconnect"],"dc:type":["Thesis"]},"updated_at":"2026-07-22T22:22:19Z"}