Energy-aware architectures, circuits and CAD for field programmable gate arrays

Field Programmable Gate Arrays (FPGAs) are a class of hardware reconfigurable logic devices based on look-up tables (LUTs) and programmable interconnect that have found broad acceptance for a wide range of applications. However, power consumption is one of the leading obstacles to broader adoption of FPGAs in energy-constrained applications. This thesis addresses active power consumption in FPGAs through the introduction of fine grain configurable power domains. By introducing fine grain power controls, sections of the design that have excess timing margins are able to run at reduced voltage thereby saving power. Delay critical sections can continue to operate at full voltage to maintain the overall performance of the design. A design flow was developed for the analysis and implementation of these configurable power domains. A test chip using dual core voltages fabricated in a 0.18 /m CMOS process features these power reduction techniques. The test chip includes an 8x8 array of logic tiles and a 9x9 switch matrix grid. The chip design flow utilizes a mix of synthesized logic and custom cells. 'The layout required a customized approach to overcome some of the challenges of implementing a fine granularity multiple voltage design.

Department dc:contributor.department

Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2006

Author dc:creator

• Honoré, Francis

Advisor dc:contributor.advisor

• Anantha P. Chandrakasan.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/37911

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/37911