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Massachusetts Institute of Technology

Multi-layer three-dimensional silicon electronics enabled by wafer bonding

Abstract

dc:description.abstract

Three-dimensional integrated circuits (3-D ICs), in the form of a vertical stack of several interconnected device layers, have many performance, form factor, and integration advantages. The main objective of this work is to develop reliable process technology to enable the fabrication of a vertically interconnected silicon multi-layer stack. Low temperature wafer bonding processes, both copper thermo-compression bonding and silicon dioxide fusion bonding, are studied extensively as key enabling technology. Cu thermo-compression bonding is studied for its feasibility as a permanent bond between active layers in a multi-layer stack. It is found that pre-bonding anneal in forming gas can remove surface oxide on Cu wafers and reduce the oxygen content in the bonded layer. The quality of bonded Cu layer is adversely degraded by the formation of interfacial voids. Void nucleation and growth are studied and counter-measures for void suppression are proposed and implemented. Silicon dioxide wafer bonding, on the other hand, is used as a temporary bond to attach a donor wafer to a handle wafer during donor wafer thinning and subsequent layer transfer. Sufficiently high bond strength is obtained with careful surface preparation and activation prior to bonding.

Degree

thesis:*
Department dc:contributor.department
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Grantor dc:publisher
Massachusetts Institute of Technology
Year dc:date.issued
2006

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Tan, Chuan Seng, Ph. D. Massachusetts Institute of Technology
Advisor dc:contributor.advisor
  • L. Rafael Reif and Anantha P. Chandrakasan.

Subjects

dc:subject × 1

Rights

dc:rights
Statement dc:rights
  • M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
Language dc:language.iso
eng

Identifiers

dc:identifier.*
Handle dc:identifier.uri
http://hdl.handle.net/1721.1/37879
OAI identifier oai:identifier
oai:dspace.mit.edu:1721.1/37879

Chain of custody

source
Harvested from
MIT
Base URL
dspace.mit.edu/oai/request
Last updated
2026-07-22
Source record
OAI-PMH GetRecord
citation

Tan, Chuan Seng, Ph. D. Massachusetts Institute of Technology. Multi-layer three-dimensional silicon electronics enabled by wafer bonding. Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/37879