The effects of excess loop delay in continuous-time sigma-delta modulators

Continuous-time sigma-delta (CT-Sigma Delta) modulators have recently received great attention in the academia as well as in the industry. Despite the improved understanding of the operation of CT-Sigma Delta modulators, the problem due to excess loop delay that arises from timing mismatch and parasitic delay still remains unsolved. Thus, the thesis investigates the effects of the excess loop delay. In specific, the sensitivity of various CT-Sigma Delta topologies to the excess loop delay is explored by converting the CT modulators to its DT equivalents and realizing loop filters in state-space representations in MATLAB ©.

Department dc:contributor.department

Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2005

Author dc:creator

• Lee, Hyunjoo Jenny

Advisor dc:contributor.advisor

• William Yang and Hae-Sung Lee.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/36787

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/36787