{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/34466"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/34466","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"The effects of strain on carrier transport in thin and ultra-thin SOI MOSFETs","abstract":"Thin-body MOSFET geometries such as fully-depleted SOI and double-gate devices are attractive because they can offer superior scaling properties compared to bulk and thick-body SOI devices. The electrostatics of a MOSFET limit how short of a gate length can be achieved before the gate loses control over the channel. In bulk-like devices, the device designer keeps the gate in control with gate oxide scaling and doping profile design. In thin-body geometries, silicon thickness is a new, powerful scaling parameter. Much like with gate oxide scaling, the electrostatics improve with thinner films. This means that the limits of scaling thin-body devices are closely tied with the limits of scaling silicon film thickness. Electrical transport appears to be one of the limiting factors for scaling body thickness. As the silicon film thickness is reduced into the ultra-thin regime, where the film is thinner than the bulk inversion layer thickness, quantum confinement effects begin to be observed. For the most part, these effects act to degrade mobility, reducing performance and making further scaling less rewarding. This work focuses on finding methods to maintain good mobility in ultra-thin silicon films. Thin and ultra-thin body relaxed SOI and biaxially strained SOI MOSFETs were constructed and measured with and without the application of mechanical uniaxial strain to examine the interaction between strain and thin-film effects.","abstract_html":"Thin-body MOSFET geometries such as fully-depleted SOI and double-gate devices are attractive because they can offer superior scaling properties compared to bulk and thick-body SOI devices. The electrostatics of a MOSFET limit how short of a gate length can be achieved before the gate loses control over the channel. In bulk-like devices, the device designer keeps the gate in control with gate oxide scaling and doping profile design. In thin-body geometries, silicon thickness is a new, powerful scaling parameter. Much like with gate oxide scaling, the electrostatics improve with thinner films. This means that the limits of scaling thin-body devices are closely tied with the limits of scaling silicon film thickness. Electrical transport appears to be one of the limiting factors for scaling body thickness. As the silicon film thickness is reduced into the ultra-thin regime, where the film is thinner than the bulk inversion layer thickness, quantum confinement effects begin to be observed. For the most part, these effects act to degrade mobility, reducing performance and making further scaling less rewarding. This work focuses on finding methods to maintain good mobility in ultra-thin silicon films. Thin and ultra-thin body relaxed SOI and biaxially strained SOI MOSFETs were constructed and measured with and without the application of mechanical uniaxial strain to examine the interaction between strain and thin-film effects.","abstract_has_math":false,"creators":["Lauer, Isaac, 1976-"],"institution":"Massachusetts Institute of Technology","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.","school":null,"contributors":[],"advisors":["Dimitri A. Antoniadis."],"committee_chairs":[],"committee_members":[],"year":2005,"date_issued":"2005","date_published":"2005","updated_at":"2026-07-22T22:22:26Z","subjects":["Electrical Engineering and Computer Science."],"languages":["eng"],"rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"rights_urls":["http://dspace.mit.edu/handle/1721.1/7582"],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/1721.1/34466","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Dimitri A. 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They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://dspace.mit.edu/handle/1721.1/7582"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/1721.1/34466"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.","Includes bibliographical references (leaves 85-91)."]},{"key":"dc:description.abstract","label":"Abstract","values":["Thin-body MOSFET geometries such as fully-depleted SOI and double-gate devices are attractive because they can offer superior scaling properties compared to bulk and thick-body SOI devices. The electrostatics of a MOSFET limit how short of a gate length can be achieved before the gate loses control over the channel. In bulk-like devices, the device designer keeps the gate in control with gate oxide scaling and doping profile design. In thin-body geometries, silicon thickness is a new, powerful scaling parameter. Much like with gate oxide scaling, the electrostatics improve with thinner films. This means that the limits of scaling thin-body devices are closely tied with the limits of scaling silicon film thickness. Electrical transport appears to be one of the limiting factors for scaling body thickness. As the silicon film thickness is reduced into the ultra-thin regime, where the film is thinner than the bulk inversion layer thickness, quantum confinement effects begin to be observed. For the most part, these effects act to degrade mobility, reducing performance and making further scaling less rewarding. This work focuses on finding methods to maintain good mobility in ultra-thin silicon films. Thin and ultra-thin body relaxed SOI and biaxially strained SOI MOSFETs were constructed and measured with and without the application of mechanical uniaxial strain to examine the interaction between strain and thin-film effects.","(cont.) The band splitting induced by the application of strain is found to at least partially mitigate the mechanisms responsible for degrading electron mobility in ultra-thin films. Additionally, the enhancement seen with uniaxial strain is found to further enhance mobility in biaxially strained films. Finally, the effective mass change caused by uniaxial strain is found to cause the mobility modulation to have a directional dependence, especially in already biaxially strained films."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["Ph.D."]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["The effects of strain on carrier transport in thin and ultra-thin SOI MOSFETs"]}]}],"canonical_facts":{"dc:contributor.advisor":["Dimitri A. Antoniadis."],"dc:contributor.department":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."],"dc:contributor.other":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."],"dc:creator":["Lauer, Isaac, 1976-"],"dc:date.accessioned":["2006-11-07T12:23:21Z"],"dc:date.available":["2006-11-07T12:23:21Z"],"dc:date.issued":["2005"],"dc:description":["Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.","Includes bibliographical references (leaves 85-91)."],"dc:description.abstract":["Thin-body MOSFET geometries such as fully-depleted SOI and double-gate devices are attractive because they can offer superior scaling properties compared to bulk and thick-body SOI devices. The electrostatics of a MOSFET limit how short of a gate length can be achieved before the gate loses control over the channel. In bulk-like devices, the device designer keeps the gate in control with gate oxide scaling and doping profile design. In thin-body geometries, silicon thickness is a new, powerful scaling parameter. Much like with gate oxide scaling, the electrostatics improve with thinner films. This means that the limits of scaling thin-body devices are closely tied with the limits of scaling silicon film thickness. Electrical transport appears to be one of the limiting factors for scaling body thickness. As the silicon film thickness is reduced into the ultra-thin regime, where the film is thinner than the bulk inversion layer thickness, quantum confinement effects begin to be observed. For the most part, these effects act to degrade mobility, reducing performance and making further scaling less rewarding. This work focuses on finding methods to maintain good mobility in ultra-thin silicon films. Thin and ultra-thin body relaxed SOI and biaxially strained SOI MOSFETs were constructed and measured with and without the application of mechanical uniaxial strain to examine the interaction between strain and thin-film effects.","(cont.) The band splitting induced by the application of strain is found to at least partially mitigate the mechanisms responsible for degrading electron mobility in ultra-thin films. Additionally, the enhancement seen with uniaxial strain is found to further enhance mobility in biaxially strained films. Finally, the effective mass change caused by uniaxial strain is found to cause the mobility modulation to have a directional dependence, especially in already biaxially strained films."],"dc:description.degree":["Ph.D."],"dc:format.mimetype":["application/pdf"],"dc:identifier.uri":["http://hdl.handle.net/1721.1/34466"],"dc:language.iso":["eng"],"dc:publisher":["Massachusetts Institute of Technology"],"dc:rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"dc:rights.uri":["http://dspace.mit.edu/handle/1721.1/7582"],"dc:subject":["Electrical Engineering and Computer Science."],"dc:title":["The effects of strain on carrier transport in thin and ultra-thin SOI MOSFETs"],"dc:type":["Thesis"]},"updated_at":"2026-07-22T22:22:26Z"}