{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/33332"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/33332","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"An optical-electrical sub-sampling down-conversion receiver with continuous-time [Sigma] [Delta] modulation","abstract":"This thesis describes the design and implementation of an optical-electrical sub-sampling down-conversion receiver that employs [Sigma] [Delta] modulation. Accurate sub-sampling of an electrical RF signal in the optical domain is achieved by using a low-jitter mode-locked-laser and a high-bandwidth interferometer. The sub-sampled information is then digitized by an optical-electrical continuous-time (CT) [Sigma] [Delta] analog- to-digital converter (ADC). Here, photodiodes and low-jitter pulses from the mode- locked-laser are leveraged to perform signal clocking and quantizer pre-amplification, overcoming digital-to-analog converter (DAC) clock jitter and quantizer metastability issues that plague traditional electronic implementations. The optical-electrical converter achieves 76.5 dB of SNR (12.4 ENOB) with a 1 MHz signal bandwidth and a sampling rate of 780 MHz. The chip was implemented using a standard bulk 0.18 [mu]m CMOS process from National Semiconductor, occupies a total area of 3 mm2, and consumes 45 mW of power.","abstract_html":"This thesis describes the design and implementation of an optical-electrical sub-sampling down-conversion receiver that employs [Sigma] [Delta] modulation. Accurate sub-sampling of an electrical RF signal in the optical domain is achieved by using a low-jitter mode-locked-laser and a high-bandwidth interferometer. The sub-sampled information is then digitized by an optical-electrical continuous-time (CT) [Sigma] [Delta] analog- to-digital converter (ADC). Here, photodiodes and low-jitter pulses from the mode- locked-laser are leveraged to perform signal clocking and quantizer pre-amplification, overcoming digital-to-analog converter (DAC) clock jitter and quantizer metastability issues that plague traditional electronic implementations. The optical-electrical converter achieves 76.5 dB of SNR (12.4 ENOB) with a 1 MHz signal bandwidth and a sampling rate of 780 MHz. The chip was implemented using a standard bulk 0.18 [mu]m CMOS process from National Semiconductor, occupies a total area of 3 mm2, and consumes 45 mW of power.","abstract_has_math":false,"creators":["Park, Matthew (Matthew J.)"],"institution":"Massachusetts Institute of Technology","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.","school":null,"contributors":[],"advisors":["Michael H. Perrott."],"committee_chairs":[],"committee_members":[],"year":2005,"date_issued":"2005","date_published":"2005","updated_at":"2026-07-22T22:21:58Z","subjects":["Electrical Engineering and Computer Science."],"languages":["eng"],"rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"rights_urls":["http://dspace.mit.edu/handle/1721.1/7582"],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/1721.1/33332","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Michael H. Perrott."]},{"key":"dc:contributor.department","label":"Department","values":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."]},{"key":"dc:contributor.other","label":"Dc Contributor Other","values":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."]},{"key":"dc:creator","label":"Author","values":["Park, Matthew (Matthew J.)"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2006-07-13T15:15:59Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2006-07-13T15:15:59Z"]},{"key":"dc:date.issued","label":"Date","values":["2005"]},{"key":"dc:publisher","label":"Institution","values":["Massachusetts Institute of Technology"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Electrical Engineering and Computer Science."]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://dspace.mit.edu/handle/1721.1/7582"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/1721.1/33332"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.","In title on t.p., [Sigma] and [Delta] appear as the upper-case Greek letters.","Includes bibliographical references (p. 87-89)."]},{"key":"dc:description.abstract","label":"Abstract","values":["This thesis describes the design and implementation of an optical-electrical sub-sampling down-conversion receiver that employs [Sigma] [Delta] modulation. Accurate sub-sampling of an electrical RF signal in the optical domain is achieved by using a low-jitter mode-locked-laser and a high-bandwidth interferometer. The sub-sampled information is then digitized by an optical-electrical continuous-time (CT) [Sigma] [Delta] analog- to-digital converter (ADC). Here, photodiodes and low-jitter pulses from the mode- locked-laser are leveraged to perform signal clocking and quantizer pre-amplification, overcoming digital-to-analog converter (DAC) clock jitter and quantizer metastability issues that plague traditional electronic implementations. The optical-electrical converter achieves 76.5 dB of SNR (12.4 ENOB) with a 1 MHz signal bandwidth and a sampling rate of 780 MHz. The chip was implemented using a standard bulk 0.18 [mu]m CMOS process from National Semiconductor, occupies a total area of 3 mm2, and consumes 45 mW of power."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["M.Eng."]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["An optical-electrical sub-sampling down-conversion receiver with continuous-time [Sigma] [Delta] modulation"]}]}],"canonical_facts":{"dc:contributor.advisor":["Michael H. Perrott."],"dc:contributor.department":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."],"dc:contributor.other":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."],"dc:creator":["Park, Matthew (Matthew J.)"],"dc:date.accessioned":["2006-07-13T15:15:59Z"],"dc:date.available":["2006-07-13T15:15:59Z"],"dc:date.issued":["2005"],"dc:description":["Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.","In title on t.p., [Sigma] and [Delta] appear as the upper-case Greek letters.","Includes bibliographical references (p. 87-89)."],"dc:description.abstract":["This thesis describes the design and implementation of an optical-electrical sub-sampling down-conversion receiver that employs [Sigma] [Delta] modulation. Accurate sub-sampling of an electrical RF signal in the optical domain is achieved by using a low-jitter mode-locked-laser and a high-bandwidth interferometer. The sub-sampled information is then digitized by an optical-electrical continuous-time (CT) [Sigma] [Delta] analog- to-digital converter (ADC). Here, photodiodes and low-jitter pulses from the mode- locked-laser are leveraged to perform signal clocking and quantizer pre-amplification, overcoming digital-to-analog converter (DAC) clock jitter and quantizer metastability issues that plague traditional electronic implementations. The optical-electrical converter achieves 76.5 dB of SNR (12.4 ENOB) with a 1 MHz signal bandwidth and a sampling rate of 780 MHz. The chip was implemented using a standard bulk 0.18 [mu]m CMOS process from National Semiconductor, occupies a total area of 3 mm2, and consumes 45 mW of power."],"dc:description.degree":["M.Eng."],"dc:format.mimetype":["application/pdf"],"dc:identifier.uri":["http://hdl.handle.net/1721.1/33332"],"dc:language.iso":["eng"],"dc:publisher":["Massachusetts Institute of Technology"],"dc:rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"dc:rights.uri":["http://dspace.mit.edu/handle/1721.1/7582"],"dc:subject":["Electrical Engineering and Computer Science."],"dc:title":["An optical-electrical sub-sampling down-conversion receiver with continuous-time [Sigma] [Delta] modulation"],"dc:type":["Thesis"]},"updated_at":"2026-07-22T22:21:58Z"}