Equivalence checking of retimed circuits

This thesis addresses the problem of verifying the equivalence of two circuits, one or both of which have undergone register retiming as well as logic resynthesis. The aim of the thesis is to improve the ability of Formality, an equivalence checking tool written at Synopsys, to handle retimed circuits. At the beginning of this project Formality already had an implementation of peripheral retiming, an algorithm that can handle a large set of retimed circuits. In this thesis, I explain the performance, usability and special case coverage problems found in the original implementation. I review other retiming verification algorithms and conclude that none of them would perform satisfactorily in Formality. Finally, I explain the modifications made to peripheral retiming in order to solve some of the identified issues and propose partial solutions for the problems that have not been solved yet.

Department dc:contributor.department

Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2005

Author dc:creator

• Netolická, Karolína

Advisor dc:contributor.advisor

• Philip Baraona and Arvind.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/32104

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/32104