{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/32094"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/32094","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"A model for analysis of the effects of redundancy and error correction on DRAM memory yield and reliability","abstract":"Manufacturing a DRAM module that is error free is a very difficult process. This process is becoming more difficult when only utilizing the current methods for producing an error free DRAM. Error correction codes (ECCs) and cell replacement are two methods currently used in isolation of each other in order to solve two of the problems with this manufacturing process: increasing reliability and increasing yield, respectively. Possible solutions to this problem are proposed and evaluated qualitatively in discussion. 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