{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/30175"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/30175","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"Synthesis and evaluation of fault-tolerant quantum computer architectures","abstract":"Fault-tolerance is the cornerstone of practical, large-scale quantum computing, pushed into its prominent position with heroic theoretical efforts. The fault-tolerance threshold, which is the component failure probability below which arbitrarily reliable quantum computation becomes possible, is one standard quality measure of fault-tolerant designs based on recursive simulation. However, there is a gulf between theoretical achievements and the physical reality and complexity of envisioned quantum computing systems. This thesis takes a step toward bridging that gap. We develop a new experimental method for estimating fault-tolerance thresholds that applies to realistic models of quantum computer architectures, and demonstrate this technique numerically. We clarify a central problem for experimental approaches to fault-tolerance evaluation--namely, distinguishing between potentially optimistic pseudo-thresholds and actual thresholds that determine scalability. Next, we create a system architecture model for the trapped-ion quantum computer, discuss potential layouts, and numerically estimate the fault-tolerance threshold for this system when it is constrained to a local layout. Finally, we place the problem of evaluation and synthesis of fault-tolerant quantum computers into a broader framework by considering a software architecture for quantum computer design.","abstract_html":"Fault-tolerance is the cornerstone of practical, large-scale quantum computing, pushed into its prominent position with heroic theoretical efforts. The fault-tolerance threshold, which is the component failure probability below which arbitrarily reliable quantum computation becomes possible, is one standard quality measure of fault-tolerant designs based on recursive simulation. However, there is a gulf between theoretical achievements and the physical reality and complexity of envisioned quantum computing systems. This thesis takes a step toward bridging that gap. We develop a new experimental method for estimating fault-tolerance thresholds that applies to realistic models of quantum computer architectures, and demonstrate this technique numerically. We clarify a central problem for experimental approaches to fault-tolerance evaluation--namely, distinguishing between potentially optimistic pseudo-thresholds and actual thresholds that determine scalability. Next, we create a system architecture model for the trapped-ion quantum computer, discuss potential layouts, and numerically estimate the fault-tolerance threshold for this system when it is constrained to a local layout. Finally, we place the problem of evaluation and synthesis of fault-tolerant quantum computers into a broader framework by considering a software architecture for quantum computer design.","abstract_has_math":false,"creators":["Cross, Andrew W. (Andrew William), 1979-"],"institution":"Massachusetts Institute of Technology","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.","school":null,"contributors":[],"advisors":["Isaac L. Chuang."],"committee_chairs":[],"committee_members":[],"year":2005,"date_issued":"2005","date_published":"2005","updated_at":"2026-07-22T22:20:47Z","subjects":["Electrical Engineering and Computer Science."],"languages":["eng"],"rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"rights_urls":["http://dspace.mit.edu/handle/1721.1/7582"],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/1721.1/30175","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Isaac L. Chuang."]},{"key":"dc:contributor.department","label":"Department","values":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."]},{"key":"dc:contributor.other","label":"Dc Contributor Other","values":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."]},{"key":"dc:creator","label":"Author","values":["Cross, Andrew W. (Andrew William), 1979-"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2006-03-24T18:26:33Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2006-03-24T18:26:33Z"]},{"key":"dc:date.issued","label":"Date","values":["2005"]},{"key":"dc:publisher","label":"Institution","values":["Massachusetts Institute of Technology"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Electrical Engineering and Computer Science."]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://dspace.mit.edu/handle/1721.1/7582"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/1721.1/30175"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.","Includes bibliographical references (p. 241-247)."]},{"key":"dc:description.abstract","label":"Abstract","values":["Fault-tolerance is the cornerstone of practical, large-scale quantum computing, pushed into its prominent position with heroic theoretical efforts. The fault-tolerance threshold, which is the component failure probability below which arbitrarily reliable quantum computation becomes possible, is one standard quality measure of fault-tolerant designs based on recursive simulation. However, there is a gulf between theoretical achievements and the physical reality and complexity of envisioned quantum computing systems. This thesis takes a step toward bridging that gap. We develop a new experimental method for estimating fault-tolerance thresholds that applies to realistic models of quantum computer architectures, and demonstrate this technique numerically. We clarify a central problem for experimental approaches to fault-tolerance evaluation--namely, distinguishing between potentially optimistic pseudo-thresholds and actual thresholds that determine scalability. Next, we create a system architecture model for the trapped-ion quantum computer, discuss potential layouts, and numerically estimate the fault-tolerance threshold for this system when it is constrained to a local layout. Finally, we place the problem of evaluation and synthesis of fault-tolerant quantum computers into a broader framework by considering a software architecture for quantum computer design."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["S.M."]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Synthesis and evaluation of fault-tolerant quantum computer architectures"]}]}],"canonical_facts":{"dc:contributor.advisor":["Isaac L. Chuang."],"dc:contributor.department":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."],"dc:contributor.other":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."],"dc:creator":["Cross, Andrew W. (Andrew William), 1979-"],"dc:date.accessioned":["2006-03-24T18:26:33Z"],"dc:date.available":["2006-03-24T18:26:33Z"],"dc:date.issued":["2005"],"dc:description":["Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.","Includes bibliographical references (p. 241-247)."],"dc:description.abstract":["Fault-tolerance is the cornerstone of practical, large-scale quantum computing, pushed into its prominent position with heroic theoretical efforts. The fault-tolerance threshold, which is the component failure probability below which arbitrarily reliable quantum computation becomes possible, is one standard quality measure of fault-tolerant designs based on recursive simulation. However, there is a gulf between theoretical achievements and the physical reality and complexity of envisioned quantum computing systems. This thesis takes a step toward bridging that gap. We develop a new experimental method for estimating fault-tolerance thresholds that applies to realistic models of quantum computer architectures, and demonstrate this technique numerically. We clarify a central problem for experimental approaches to fault-tolerance evaluation--namely, distinguishing between potentially optimistic pseudo-thresholds and actual thresholds that determine scalability. Next, we create a system architecture model for the trapped-ion quantum computer, discuss potential layouts, and numerically estimate the fault-tolerance threshold for this system when it is constrained to a local layout. Finally, we place the problem of evaluation and synthesis of fault-tolerant quantum computers into a broader framework by considering a software architecture for quantum computer design."],"dc:description.degree":["S.M."],"dc:format.mimetype":["application/pdf"],"dc:identifier.uri":["http://hdl.handle.net/1721.1/30175"],"dc:language.iso":["eng"],"dc:publisher":["Massachusetts Institute of Technology"],"dc:rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"dc:rights.uri":["http://dspace.mit.edu/handle/1721.1/7582"],"dc:subject":["Electrical Engineering and Computer Science."],"dc:title":["Synthesis and evaluation of fault-tolerant quantum computer architectures"],"dc:type":["Thesis"]},"updated_at":"2026-07-22T22:20:47Z"}