{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/29683"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/29683","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"A high-speed cascaded folding and interpolating A/D converter","abstract":"The folding and interpolating technique has been introduced to CMOS analog-to- digital converter (ADC) in the 1980's. It has successfully reduced the number of comparators required while preserving the benefits of a flash ADC. However, similar to flash ADC, folding and interpolating ADC is also limited to low resolution, due to its complication in the folding operation. Cascaded folding and interpolating architecture is then adopted to alleviate the problem. The design of a 10-bit, 55MSPS ADC is presented to illustrate the merits of the architecture. Data conversion is conducted in two parallel blocks, the MSB and LSB sections. The MSB section is responsible for computing the four MSBs while the LSB section computes the remaining six LSBs. The folding and interpolation preprocessing, completed in three cascaded stages, is employed in the LSB section. The circuit functions are designed in 0.35[mu]m CMOS process with a 3.3V supply. The analog circuitry dissipates 54m W while achieving < 1 /2 LSB DNL performance in simulation.","abstract_html":"The folding and interpolating technique has been introduced to CMOS analog-to- digital converter (ADC) in the 1980&#x27;s. It has successfully reduced the number of comparators required while preserving the benefits of a flash ADC. However, similar to flash ADC, folding and interpolating ADC is also limited to low resolution, due to its complication in the folding operation. Cascaded folding and interpolating architecture is then adopted to alleviate the problem. The design of a 10-bit, 55MSPS ADC is presented to illustrate the merits of the architecture. Data conversion is conducted in two parallel blocks, the MSB and LSB sections. The MSB section is responsible for computing the four MSBs while the LSB section computes the remaining six LSBs. The folding and interpolation preprocessing, completed in three cascaded stages, is employed in the LSB section. The circuit functions are designed in 0.35[mu]m CMOS process with a 3.3V supply. The analog circuitry dissipates 54m W while achieving &lt; 1 /2 LSB DNL performance in simulation.","abstract_has_math":false,"creators":["Lau, Yanlok Charlotte, 1979-"],"institution":"Massachusetts Institute of Technology","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.","school":null,"contributors":[],"advisors":["William Yang and James K. Roberge."],"committee_chairs":[],"committee_members":[],"year":2003,"date_issued":"2003","date_published":"2003","updated_at":"2026-07-22T22:22:13Z","subjects":["Electrical Engineering and Computer Science."],"languages":["eng"],"rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"rights_urls":["http://dspace.mit.edu/handle/1721.1/7582"],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/1721.1/29683","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["William Yang and James K. Roberge."]},{"key":"dc:contributor.department","label":"Department","values":["Massachusetts Institute of Technology. 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It has successfully reduced the number of comparators required while preserving the benefits of a flash ADC. However, similar to flash ADC, folding and interpolating ADC is also limited to low resolution, due to its complication in the folding operation. Cascaded folding and interpolating architecture is then adopted to alleviate the problem. The design of a 10-bit, 55MSPS ADC is presented to illustrate the merits of the architecture. Data conversion is conducted in two parallel blocks, the MSB and LSB sections. The MSB section is responsible for computing the four MSBs while the LSB section computes the remaining six LSBs. The folding and interpolation preprocessing, completed in three cascaded stages, is employed in the LSB section. The circuit functions are designed in 0.35[mu]m CMOS process with a 3.3V supply. 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Data conversion is conducted in two parallel blocks, the MSB and LSB sections. The MSB section is responsible for computing the four MSBs while the LSB section computes the remaining six LSBs. The folding and interpolation preprocessing, completed in three cascaded stages, is employed in the LSB section. The circuit functions are designed in 0.35[mu]m CMOS process with a 3.3V supply. The analog circuitry dissipates 54m W while achieving < 1 /2 LSB DNL performance in simulation."],"dc:description.degree":["M.Eng."],"dc:format.mimetype":["application/pdf"],"dc:identifier.uri":["http://hdl.handle.net/1721.1/29683"],"dc:language.iso":["eng"],"dc:publisher":["Massachusetts Institute of Technology"],"dc:rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"dc:rights.uri":["http://dspace.mit.edu/handle/1721.1/7582"],"dc:subject":["Electrical Engineering and Computer Science."],"dc:title":["A high-speed cascaded folding and interpolating A/D converter"],"dc:type":["Thesis"]},"updated_at":"2026-07-22T22:22:13Z"}