{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/28548"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/28548","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"Post assembly process development for Monolithic OptoPill integration on silicon CMOS","abstract":"Monolithic OptoPill integration by means of recess mounting is a heterogeneous technique employed to integrate III-V photonic devices on silicon CMOS circuits. The goal is to create an effective fabrication process that enables the volume production of high performance optoelectronic integrated circuits (OEICs). This thesis focuses on the development of post-assembly processes and technologies, in which InGaAs/InP P-i-N photodiodes were integrated as long wavelength photodetectors with an optical clock receiver circuit. Fabrication procedures, challenges experienced, and results accomplished are presented for each process step including the formation of alloyed and non-alloyed ohmic contacts on n-type and p-type InGaAs contact layers, active area definition by dry-etching InGaAs/InP with ECR-enhanced RIE, BCB passivation and planarization, via opening by dry-etching BCB with RIE, and top contact metallization. In conjunction, an InP-based test heterostructure was fabricated into discrete photodiodes. Decoupling the fabrication and benchmarking of III-V photonic device from the Si-CMOS electronic circuit allowed for the independent electrical and optical characterization of the photodetectors. Measurements and analysis of the P-i-N photodiodes will assist the forthcoming analysis of the final OEIC. Preliminary results and discussions of the calibration sample are presented in this thesis.","abstract_html":"Monolithic OptoPill integration by means of recess mounting is a heterogeneous technique employed to integrate III-V photonic devices on silicon CMOS circuits. The goal is to create an effective fabrication process that enables the volume production of high performance optoelectronic integrated circuits (OEICs). This thesis focuses on the development of post-assembly processes and technologies, in which InGaAs/InP P-i-N photodiodes were integrated as long wavelength photodetectors with an optical clock receiver circuit. Fabrication procedures, challenges experienced, and results accomplished are presented for each process step including the formation of alloyed and non-alloyed ohmic contacts on n-type and p-type InGaAs contact layers, active area definition by dry-etching InGaAs/InP with ECR-enhanced RIE, BCB passivation and planarization, via opening by dry-etching BCB with RIE, and top contact metallization. In conjunction, an InP-based test heterostructure was fabricated into discrete photodiodes. Decoupling the fabrication and benchmarking of III-V photonic device from the Si-CMOS electronic circuit allowed for the independent electrical and optical characterization of the photodetectors. Measurements and analysis of the P-i-N photodiodes will assist the forthcoming analysis of the final OEIC. Preliminary results and discussions of the calibration sample are presented in this thesis.","abstract_has_math":false,"creators":["Lei, Yi-Shu Vivian, 1979-"],"institution":"Massachusetts Institute of Technology","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.","school":null,"contributors":[],"advisors":["Clifton G. Fonstad, Jr."],"committee_chairs":[],"committee_members":[],"year":2004,"date_issued":"2004","date_published":"2004","updated_at":"2026-07-22T22:21:19Z","subjects":["Electrical Engineering and Computer Science."],"languages":["en_US"],"rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"rights_urls":["http://dspace.mit.edu/handle/1721.1/7582"],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/1721.1/28548","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Clifton G. Fonstad, Jr."]},{"key":"dc:contributor.department","label":"Department","values":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."]},{"key":"dc:contributor.other","label":"Dc Contributor Other","values":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."]},{"key":"dc:creator","label":"Author","values":["Lei, Yi-Shu Vivian, 1979-"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2005-09-27T16:56:40Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2005-09-27T16:56:40Z"]},{"key":"dc:date.issued","label":"Date","values":["2004"]},{"key":"dc:publisher","label":"Institution","values":["Massachusetts Institute of Technology"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Electrical Engineering and Computer Science."]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en_US"]},{"key":"dc:rights","label":"Dc Rights","values":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://dspace.mit.edu/handle/1721.1/7582"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/1721.1/28548"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.","Includes bibliographical references (leaves 108-110)."]},{"key":"dc:description.abstract","label":"Abstract","values":["Monolithic OptoPill integration by means of recess mounting is a heterogeneous technique employed to integrate III-V photonic devices on silicon CMOS circuits. The goal is to create an effective fabrication process that enables the volume production of high performance optoelectronic integrated circuits (OEICs). This thesis focuses on the development of post-assembly processes and technologies, in which InGaAs/InP P-i-N photodiodes were integrated as long wavelength photodetectors with an optical clock receiver circuit. Fabrication procedures, challenges experienced, and results accomplished are presented for each process step including the formation of alloyed and non-alloyed ohmic contacts on n-type and p-type InGaAs contact layers, active area definition by dry-etching InGaAs/InP with ECR-enhanced RIE, BCB passivation and planarization, via opening by dry-etching BCB with RIE, and top contact metallization. In conjunction, an InP-based test heterostructure was fabricated into discrete photodiodes. Decoupling the fabrication and benchmarking of III-V photonic device from the Si-CMOS electronic circuit allowed for the independent electrical and optical characterization of the photodetectors. Measurements and analysis of the P-i-N photodiodes will assist the forthcoming analysis of the final OEIC. Preliminary results and discussions of the calibration sample are presented in this thesis."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["S.M."]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Post assembly process development for Monolithic OptoPill integration on silicon CMOS"]}]}],"canonical_facts":{"dc:contributor.advisor":["Clifton G. Fonstad, Jr."],"dc:contributor.department":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."],"dc:contributor.other":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."],"dc:creator":["Lei, Yi-Shu Vivian, 1979-"],"dc:date.accessioned":["2005-09-27T16:56:40Z"],"dc:date.available":["2005-09-27T16:56:40Z"],"dc:date.issued":["2004"],"dc:description":["Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.","Includes bibliographical references (leaves 108-110)."],"dc:description.abstract":["Monolithic OptoPill integration by means of recess mounting is a heterogeneous technique employed to integrate III-V photonic devices on silicon CMOS circuits. The goal is to create an effective fabrication process that enables the volume production of high performance optoelectronic integrated circuits (OEICs). This thesis focuses on the development of post-assembly processes and technologies, in which InGaAs/InP P-i-N photodiodes were integrated as long wavelength photodetectors with an optical clock receiver circuit. Fabrication procedures, challenges experienced, and results accomplished are presented for each process step including the formation of alloyed and non-alloyed ohmic contacts on n-type and p-type InGaAs contact layers, active area definition by dry-etching InGaAs/InP with ECR-enhanced RIE, BCB passivation and planarization, via opening by dry-etching BCB with RIE, and top contact metallization. In conjunction, an InP-based test heterostructure was fabricated into discrete photodiodes. Decoupling the fabrication and benchmarking of III-V photonic device from the Si-CMOS electronic circuit allowed for the independent electrical and optical characterization of the photodetectors. Measurements and analysis of the P-i-N photodiodes will assist the forthcoming analysis of the final OEIC. Preliminary results and discussions of the calibration sample are presented in this thesis."],"dc:description.degree":["S.M."],"dc:format.mimetype":["application/pdf"],"dc:identifier.uri":["http://hdl.handle.net/1721.1/28548"],"dc:language.iso":["en_US"],"dc:publisher":["Massachusetts Institute of Technology"],"dc:rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"dc:rights.uri":["http://dspace.mit.edu/handle/1721.1/7582"],"dc:subject":["Electrical Engineering and Computer Science."],"dc:title":["Post assembly process development for Monolithic OptoPill integration on silicon CMOS"],"dc:type":["Thesis"]},"updated_at":"2026-07-22T22:21:19Z"}