{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/28491"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/28491","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"Rapid fabrication of deep-submicron Josephson junctions","abstract":"A process was designed to fabricate Nb-AlOx-Nb Josephson junctions for quantum computing applications, with the goal of fabricating junctions as small as 0.2 [micro]m in diameter in a time span of roughly two weeks. The process was based on the doubly-planarized all-refractory technology for superconductive circuits (DPARTS) process currently used to fabricate these devices at MIT Lincoln Laboratory and streamlined by removing or replacing the most time-consuming steps and several optical layers. In addition, 248-nm (deep-UV) photolithography was employed for the first time in a Nb-based process, with the goal of improving resolution past that achievable by standard i-line lithography. The process has five optical layers, two wiring layers, and a via layer, and is intended to be used for rapid-turnaround evaluation of simple circuits requiring only two wiring layers. Anodization was used to produce a 50 nm film of NbOx to isolate the wiring layers, replacing the time-consuming oxide deposition and planarization used in the DPARTS process. A novel metallization and liftoff process employing surface-poisoning of chemically-amplified resist was used to deposit the contact layer. Several new plasma etching techniques were developed to selectively etch the various materials present in the process as well. The full process flow is briefly described in order of fabrication, followed by a detailed discussion of major process steps, issues, and results. Finally, testing results from devices fabricated using the new process are presented. An appendix detailing the design-of-experiment (DOE) approach used to characterize several process tools is also provided.","abstract_html":"A process was designed to fabricate Nb-AlOx-Nb Josephson junctions for quantum computing applications, with the goal of fabricating junctions as small as 0.2 [micro]m in diameter in a time span of roughly two weeks. The process was based on the doubly-planarized all-refractory technology for superconductive circuits (DPARTS) process currently used to fabricate these devices at MIT Lincoln Laboratory and streamlined by removing or replacing the most time-consuming steps and several optical layers. In addition, 248-nm (deep-UV) photolithography was employed for the first time in a Nb-based process, with the goal of improving resolution past that achievable by standard i-line lithography. The process has five optical layers, two wiring layers, and a via layer, and is intended to be used for rapid-turnaround evaluation of simple circuits requiring only two wiring layers. Anodization was used to produce a 50 nm film of NbOx to isolate the wiring layers, replacing the time-consuming oxide deposition and planarization used in the DPARTS process. A novel metallization and liftoff process employing surface-poisoning of chemically-amplified resist was used to deposit the contact layer. Several new plasma etching techniques were developed to selectively etch the various materials present in the process as well. The full process flow is briefly described in order of fabrication, followed by a detailed discussion of major process steps, issues, and results. Finally, testing results from devices fabricated using the new process are presented. An appendix detailing the design-of-experiment (DOE) approach used to characterize several process tools is also provided.","abstract_has_math":false,"creators":["Cord, Bryan M. (Bryan Michael), 1980-"],"institution":"Massachusetts Institute of Technology","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.","school":null,"contributors":[],"advisors":["Terry P. Orlando."],"committee_chairs":[],"committee_members":[],"year":2004,"date_issued":"2004","date_published":"2004","updated_at":"2026-07-22T22:22:19Z","subjects":["Electrical Engineering and Computer Science."],"languages":["en_US"],"rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"rights_urls":["http://dspace.mit.edu/handle/1721.1/7582"],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/1721.1/28491","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Terry P. Orlando."]},{"key":"dc:contributor.department","label":"Department","values":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."]},{"key":"dc:contributor.other","label":"Dc Contributor Other","values":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."]},{"key":"dc:creator","label":"Author","values":["Cord, Bryan M. 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The process was based on the doubly-planarized all-refractory technology for superconductive circuits (DPARTS) process currently used to fabricate these devices at MIT Lincoln Laboratory and streamlined by removing or replacing the most time-consuming steps and several optical layers. In addition, 248-nm (deep-UV) photolithography was employed for the first time in a Nb-based process, with the goal of improving resolution past that achievable by standard i-line lithography. The process has five optical layers, two wiring layers, and a via layer, and is intended to be used for rapid-turnaround evaluation of simple circuits requiring only two wiring layers. Anodization was used to produce a 50 nm film of NbOx to isolate the wiring layers, replacing the time-consuming oxide deposition and planarization used in the DPARTS process. A novel metallization and liftoff process employing surface-poisoning of chemically-amplified resist was used to deposit the contact layer. Several new plasma etching techniques were developed to selectively etch the various materials present in the process as well. The full process flow is briefly described in order of fabrication, followed by a detailed discussion of major process steps, issues, and results. Finally, testing results from devices fabricated using the new process are presented. An appendix detailing the design-of-experiment (DOE) approach used to characterize several process tools is also provided."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["S.M."]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Rapid fabrication of deep-submicron Josephson junctions"]}]}],"canonical_facts":{"dc:contributor.advisor":["Terry P. Orlando."],"dc:contributor.department":["Massachusetts Institute of Technology. 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The process was based on the doubly-planarized all-refractory technology for superconductive circuits (DPARTS) process currently used to fabricate these devices at MIT Lincoln Laboratory and streamlined by removing or replacing the most time-consuming steps and several optical layers. In addition, 248-nm (deep-UV) photolithography was employed for the first time in a Nb-based process, with the goal of improving resolution past that achievable by standard i-line lithography. The process has five optical layers, two wiring layers, and a via layer, and is intended to be used for rapid-turnaround evaluation of simple circuits requiring only two wiring layers. Anodization was used to produce a 50 nm film of NbOx to isolate the wiring layers, replacing the time-consuming oxide deposition and planarization used in the DPARTS process. A novel metallization and liftoff process employing surface-poisoning of chemically-amplified resist was used to deposit the contact layer. Several new plasma etching techniques were developed to selectively etch the various materials present in the process as well. The full process flow is briefly described in order of fabrication, followed by a detailed discussion of major process steps, issues, and results. Finally, testing results from devices fabricated using the new process are presented. An appendix detailing the design-of-experiment (DOE) approach used to characterize several process tools is also provided."],"dc:description.degree":["S.M."],"dc:format.mimetype":["application/pdf"],"dc:identifier.uri":["http://hdl.handle.net/1721.1/28491"],"dc:language.iso":["en_US"],"dc:publisher":["Massachusetts Institute of Technology"],"dc:rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"dc:rights.uri":["http://dspace.mit.edu/handle/1721.1/7582"],"dc:subject":["Electrical Engineering and Computer Science."],"dc:title":["Rapid fabrication of deep-submicron Josephson junctions"],"dc:type":["Thesis"]},"updated_at":"2026-07-22T22:22:19Z"}