{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/28380"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/28380","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"Fast offset compensation for a 10Gbps limit amplifier","abstract":"A novel offset voltage compensation method is presented that significantly modifies the existing tradeoff between control loop bandwidth, and therefore total compensation time, and total output jitter. The proposed system achieves comparable output jitter performance to traditional approaches while significantly reducing the total compensation time by nearly three orders of magnitude. Traditional offset compensation methods are based on simple offset measurement techniques that generally rely on passive compensation blocks and exhibit a direct inverse relationship between total compensation time and resulting output jitter. Therefore, current high-speed data-link systems suffer from extremely long offset compensation loop settling times in order to satisfy the strict protocol jitter specifications. In the proposed system, the new CMOS peak detector design is the enabling component that allows us break this relationship and achieve extremely fast settling behavior while preventing data dependence of the control signal. Simulated results show that the implemented system can achieve output jitter performance similar to existing methods while dramatically improving the compensation time. Specifically, the proposed system can achieve less than 2pS of peak-to-peak jitter, or less than 700fS of RMS jitter, while reducing the total compensation time from roughly 500[mu]S to less than 1[mu]S. The system was implemented in National Semiconductor's CMOS9 0.18[mu]m CMOS process. Packaged parts will be tested to verify agreement with simulated performance.","abstract_html":"A novel offset voltage compensation method is presented that significantly modifies the existing tradeoff between control loop bandwidth, and therefore total compensation time, and total output jitter. The proposed system achieves comparable output jitter performance to traditional approaches while significantly reducing the total compensation time by nearly three orders of magnitude. Traditional offset compensation methods are based on simple offset measurement techniques that generally rely on passive compensation blocks and exhibit a direct inverse relationship between total compensation time and resulting output jitter. Therefore, current high-speed data-link systems suffer from extremely long offset compensation loop settling times in order to satisfy the strict protocol jitter specifications. In the proposed system, the new CMOS peak detector design is the enabling component that allows us break this relationship and achieve extremely fast settling behavior while preventing data dependence of the control signal. Simulated results show that the implemented system can achieve output jitter performance similar to existing methods while dramatically improving the compensation time. Specifically, the proposed system can achieve less than 2pS of peak-to-peak jitter, or less than 700fS of RMS jitter, while reducing the total compensation time from roughly 500[mu]S to less than 1[mu]S. The system was implemented in National Semiconductor's CMOS9 0.18[mu]m CMOS process. Packaged parts will be tested to verify agreement with simulated performance.","abstract_has_math":false,"creators":["Crain, Ethan A. (Ethan Alan), 1972-"],"institution":"Massachusetts Institute of Technology","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.","school":null,"contributors":[],"advisors":["Michael H. Perrott."],"committee_chairs":[],"committee_members":[],"year":2004,"date_issued":"2004","date_published":"2004","updated_at":"2026-07-22T22:21:22Z","subjects":["Electrical Engineering and Computer Science."],"languages":["en_US"],"rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. 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Therefore, current high-speed data-link systems suffer from extremely long offset compensation loop settling times in order to satisfy the strict protocol jitter specifications. In the proposed system, the new CMOS peak detector design is the enabling component that allows us break this relationship and achieve extremely fast settling behavior while preventing data dependence of the control signal. Simulated results show that the implemented system can achieve output jitter performance similar to existing methods while dramatically improving the compensation time. Specifically, the proposed system can achieve less than 2pS of peak-to-peak jitter, or less than 700fS of RMS jitter, while reducing the total compensation time from roughly 500[mu]S to less than 1[mu]S. The system was implemented in National Semiconductor's CMOS9 0.18[mu]m CMOS process. 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In the proposed system, the new CMOS peak detector design is the enabling component that allows us break this relationship and achieve extremely fast settling behavior while preventing data dependence of the control signal. Simulated results show that the implemented system can achieve output jitter performance similar to existing methods while dramatically improving the compensation time. Specifically, the proposed system can achieve less than 2pS of peak-to-peak jitter, or less than 700fS of RMS jitter, while reducing the total compensation time from roughly 500[mu]S to less than 1[mu]S. The system was implemented in National Semiconductor's CMOS9 0.18[mu]m CMOS process. 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