{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/18060"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/18060","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"Analysis of DRIE uniformity for microelectromechanical systems","abstract":"A quantitative model capturing pattern density effects in Deep Reactive Ion Etch (DRIE), which are important in MEMS, is presented. Our previous work has explored the causes of wafer-level variation and demonstrated die-to-die interactions resulting from pattern density and reactant species consumption. Several reports have focused on experimental evidence and modeling of feature level (aspect ratio) dependencies. This thesis contributes a computationally efficient and effective modeling approach which focuses on layout pattern density-induced nonuniformity in DRIE. This is a key component in an integrated model combining wafer-, die-, and feature-level DRIE dependencies to predict etch depth for an input layout and a characterized etch tool and process. The modeling approach proposed here is inspired by previous work in modeling of chemical mechanical polishing (CMP). Computationally, this involves the convolution of an etch \"layout impulse response\" function or filter with the layout information (or equivalently but more efficiently the multiplication of FFTs). The proposed model is validated by using a mask layer from the MIT Microengine project as a demonstration layout. The model can be tuned to predict the etch behavior to an accuracy of 0.1% RMS normalized error. Furthermore, a feature level model, which considers the effects of sidewall loading on the depletion of reactants is presented. Finally, methods of synthesizing dummy features to improve across-die uniformity in a layout are explored; a by tiling bare areas of the wafer into \"fill zones,\" an improvement in intra-die uniformity is seen. In summary, a semi-empirical modeling approach has been developed for predicting the layout dependent pattern density nonuniformities present","abstract_html":"A quantitative model capturing pattern density effects in Deep Reactive Ion Etch (DRIE), which are important in MEMS, is presented. Our previous work has explored the causes of wafer-level variation and demonstrated die-to-die interactions resulting from pattern density and reactant species consumption. Several reports have focused on experimental evidence and modeling of feature level (aspect ratio) dependencies. This thesis contributes a computationally efficient and effective modeling approach which focuses on layout pattern density-induced nonuniformity in DRIE. This is a key component in an integrated model combining wafer-, die-, and feature-level DRIE dependencies to predict etch depth for an input layout and a characterized etch tool and process. The modeling approach proposed here is inspired by previous work in modeling of chemical mechanical polishing (CMP). Computationally, this involves the convolution of an etch "layout impulse response" function or filter with the layout information (or equivalently but more efficiently the multiplication of FFTs). The proposed model is validated by using a mask layer from the MIT Microengine project as a demonstration layout. The model can be tuned to predict the etch behavior to an accuracy of 0.1% RMS normalized error. Furthermore, a feature level model, which considers the effects of sidewall loading on the depletion of reactants is presented. Finally, methods of synthesizing dummy features to improve across-die uniformity in a layout are explored; a by tiling bare areas of the wafer into "fill zones," an improvement in intra-die uniformity is seen. In summary, a semi-empirical modeling approach has been developed for predicting the layout dependent pattern density nonuniformities present","abstract_has_math":false,"creators":["Hill, Tyrone F. (Tyrone Frank), 1980-"],"institution":"Massachusetts Institute of Technology","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.","school":null,"contributors":[],"advisors":["Duane S. Boning."],"committee_chairs":[],"committee_members":[],"year":2004,"date_issued":"2004","date_published":"2004","updated_at":"2026-07-22T22:20:52Z","subjects":["Electrical Engineering and Computer Science."],"languages":["eng"],"rights":["M.I.T. theses are protected by copyright. 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Our previous work has explored the causes of wafer-level variation and demonstrated die-to-die interactions resulting from pattern density and reactant species consumption. Several reports have focused on experimental evidence and modeling of feature level (aspect ratio) dependencies. This thesis contributes a computationally efficient and effective modeling approach which focuses on layout pattern density-induced nonuniformity in DRIE. This is a key component in an integrated model combining wafer-, die-, and feature-level DRIE dependencies to predict etch depth for an input layout and a characterized etch tool and process. The modeling approach proposed here is inspired by previous work in modeling of chemical mechanical polishing (CMP). Computationally, this involves the convolution of an etch \"layout impulse response\" function or filter with the layout information (or equivalently but more efficiently the multiplication of FFTs). The proposed model is validated by using a mask layer from the MIT Microengine project as a demonstration layout. The model can be tuned to predict the etch behavior to an accuracy of 0.1% RMS normalized error. Furthermore, a feature level model, which considers the effects of sidewall loading on the depletion of reactants is presented. Finally, methods of synthesizing dummy features to improve across-die uniformity in a layout are explored; a by tiling bare areas of the wafer into \"fill zones,\" an improvement in intra-die uniformity is seen. In summary, a semi-empirical modeling approach has been developed for predicting the layout dependent pattern density nonuniformities present","(cont.) in DRIE. The approach can be tuned to specific tools and processes, and is computationally efficient. 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This is a key component in an integrated model combining wafer-, die-, and feature-level DRIE dependencies to predict etch depth for an input layout and a characterized etch tool and process. The modeling approach proposed here is inspired by previous work in modeling of chemical mechanical polishing (CMP). Computationally, this involves the convolution of an etch \"layout impulse response\" function or filter with the layout information (or equivalently but more efficiently the multiplication of FFTs). The proposed model is validated by using a mask layer from the MIT Microengine project as a demonstration layout. The model can be tuned to predict the etch behavior to an accuracy of 0.1% RMS normalized error. Furthermore, a feature level model, which considers the effects of sidewall loading on the depletion of reactants is presented. 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