{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/17998"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/17998","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"Threshold voltage in pentacene field effect transistors with parylene dielectric","abstract":"Organic field effect transistors (OFETs) offer a suitable building block for many flexible, large-area applications such as display backplanes, electronic textiles, and robotic skin. Besides the organic semiconductor itself, an important area in the development of OFETs is the gate dielectric material. In this thesis the organic polymer parylene is studied as a gate dielectric for pentacene OFETs. The three main areas of study were: (1) parylene's performance as a dielectric, (2) possible improvement of OFETs by surface treatments, and (3) the effects of interface traps on threshold voltage and parasitic bulk conductivity. Parylene was found to provide a favorable, hydrophobic interface for pentacene growth, yielding transistors with mobilities > 0.5cm²/Vs at -100V. While the two surface treatments explored did increase contact angle by 10-20⁰, neither the ammonium sulfide nor the polystyrene treatment significantly improved pentacene packing or mobility. Modification of the parylene surface using an oxygen plasma introduced traps at the semiconductor-dielectric interface, observable through a variety of characterization techniques. A model is developed to explain how the fixed and mobile charges these traps introduce influence the threshold voltage and parasitic conductivity in the device.","abstract_html":"Organic field effect transistors (OFETs) offer a suitable building block for many flexible, large-area applications such as display backplanes, electronic textiles, and robotic skin. Besides the organic semiconductor itself, an important area in the development of OFETs is the gate dielectric material. In this thesis the organic polymer parylene is studied as a gate dielectric for pentacene OFETs. The three main areas of study were: (1) parylene's performance as a dielectric, (2) possible improvement of OFETs by surface treatments, and (3) the effects of interface traps on threshold voltage and parasitic bulk conductivity. Parylene was found to provide a favorable, hydrophobic interface for pentacene growth, yielding transistors with mobilities > 0.5cm²/Vs at -100V. While the two surface treatments explored did increase contact angle by 10-20⁰, neither the ammonium sulfide nor the polystyrene treatment significantly improved pentacene packing or mobility. Modification of the parylene surface using an oxygen plasma introduced traps at the semiconductor-dielectric interface, observable through a variety of characterization techniques. A model is developed to explain how the fixed and mobile charges these traps introduce influence the threshold voltage and parasitic conductivity in the device.","abstract_has_math":false,"creators":["Wang, Annie I. (Annie I-Jen), 1981-"],"institution":"Massachusetts Institute of Technology","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.","school":null,"contributors":[],"advisors":["Akintunde Akinwande and Ioannis Kymissis."],"committee_chairs":[],"committee_members":[],"year":2004,"date_issued":"2004","date_published":"2004","updated_at":"2026-07-22T22:22:07Z","subjects":["Electrical Engineering and Computer Science."],"languages":["eng"],"rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"rights_urls":["http://dspace.mit.edu/handle/1721.1/7582"],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/1721.1/17998","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Akintunde Akinwande and Ioannis Kymissis."]},{"key":"dc:contributor.department","label":"Department","values":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."]},{"key":"dc:contributor.other","label":"Dc Contributor Other","values":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."]},{"key":"dc:creator","label":"Author","values":["Wang, Annie I. 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Besides the organic semiconductor itself, an important area in the development of OFETs is the gate dielectric material. In this thesis the organic polymer parylene is studied as a gate dielectric for pentacene OFETs. The three main areas of study were: (1) parylene's performance as a dielectric, (2) possible improvement of OFETs by surface treatments, and (3) the effects of interface traps on threshold voltage and parasitic bulk conductivity. Parylene was found to provide a favorable, hydrophobic interface for pentacene growth, yielding transistors with mobilities > 0.5cm²/Vs at -100V. While the two surface treatments explored did increase contact angle by 10-20⁰, neither the ammonium sulfide nor the polystyrene treatment significantly improved pentacene packing or mobility. Modification of the parylene surface using an oxygen plasma introduced traps at the semiconductor-dielectric interface, observable through a variety of characterization techniques. A model is developed to explain how the fixed and mobile charges these traps introduce influence the threshold voltage and parasitic conductivity in the device."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["M.Eng.and S.B."]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Threshold voltage in pentacene field effect transistors with parylene dielectric"]}]}],"canonical_facts":{"dc:contributor.advisor":["Akintunde Akinwande and Ioannis Kymissis."],"dc:contributor.department":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."],"dc:contributor.other":["Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science."],"dc:creator":["Wang, Annie I. (Annie I-Jen), 1981-"],"dc:date.accessioned":["2005-06-02T19:34:01Z"],"dc:date.available":["2005-06-02T19:34:01Z"],"dc:date.issued":["2004"],"dc:description":["Thesis (M. Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.","Includes bibliographical references (p. 59-63)."],"dc:description.abstract":["Organic field effect transistors (OFETs) offer a suitable building block for many flexible, large-area applications such as display backplanes, electronic textiles, and robotic skin. Besides the organic semiconductor itself, an important area in the development of OFETs is the gate dielectric material. In this thesis the organic polymer parylene is studied as a gate dielectric for pentacene OFETs. The three main areas of study were: (1) parylene's performance as a dielectric, (2) possible improvement of OFETs by surface treatments, and (3) the effects of interface traps on threshold voltage and parasitic bulk conductivity. Parylene was found to provide a favorable, hydrophobic interface for pentacene growth, yielding transistors with mobilities > 0.5cm²/Vs at -100V. While the two surface treatments explored did increase contact angle by 10-20⁰, neither the ammonium sulfide nor the polystyrene treatment significantly improved pentacene packing or mobility. Modification of the parylene surface using an oxygen plasma introduced traps at the semiconductor-dielectric interface, observable through a variety of characterization techniques. A model is developed to explain how the fixed and mobile charges these traps introduce influence the threshold voltage and parasitic conductivity in the device."],"dc:description.degree":["M.Eng.and S.B."],"dc:format.mimetype":["application/pdf"],"dc:identifier.uri":["http://hdl.handle.net/1721.1/17998"],"dc:language.iso":["eng"],"dc:publisher":["Massachusetts Institute of Technology"],"dc:rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"dc:rights.uri":["http://dspace.mit.edu/handle/1721.1/7582"],"dc:subject":["Electrical Engineering and Computer Science."],"dc:title":["Threshold voltage in pentacene field effect transistors with parylene dielectric"],"dc:type":["Thesis"]},"updated_at":"2026-07-22T22:22:07Z"}