WSIM configurable digital signal processor simulator/debugger

This M.Eng. Thesis presents a design and implementation of a full-featured configurable Digital Signal Processor (DSP) simulator/debugger. The user will be able to set configurations in order to model a specific architecture design. The simulator will have a command interpreter to listen to and process commands given by the user. When supplied with an assembly program, the simulator will allow the user to step through the execution of the program cycle by cycle, as well as calculate statistics like instruction, resource, and cache profiling. Some of the main features of the simulator are a multiply-accumulate unit, memory with direct and indirect offset addressing, and loop instructions.

Department dc:contributor.department

Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2004

Author dc:creator

• Ni, Wayland, 1982-

Advisor dc:contributor.advisor

• Charlie Sakamaki and Chris Terman.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/16683

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/16683