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Massachusetts Institute of Technology

Reconfigurable and Interference-Tolerant Receivers for Next Generation Wireless Systems

Abstract

dc:description.abstract

An “all-in-one” radio, programmable across the sub-7 GHz spectrum, offers significant hardware efficiency for 5G systems. However, addressing strong interferers in this wide and congested spectrum remains a major design challenge. N-path filters offer a promising solution for efficiently suppressing interference, thanks to their clock-controlled reconfigurability and excellent linearity against in-band and adjacent-channel blockers. While widely adopted in modern receiver architectures, these switched-capacitor circuits remain inherently vulnerable to blockers at clock harmonics, due to their hard-switching nature. These blockers, common in 5G bands, pose a key bottleneck, delaying the realization of fully integrated multi-band, multi-mode radios. This dissertation introduces fully passive topologies to address this challenge. The first design leverages simultaneous charge sharing and capacitor stacking to implement harmonic rejection filtering. It operates entirely without active circuitry and exhibits exceptionally low loss. A second-generation technique, termed “harmonic reset switching”, builds on this approach by rejecting harmonic blockers directly at the driving point of the N-path filter, achieving superior performance with reduced circuit complexity. As a result, existing reconfigurable receiver topologies can be seamlessly transformed into harmonic blocker–resilient architectures. For example, a taped-out mixer-first receiver adopting this technique achieves a 100× improvement in third-harmonic blocker tolerance compared to state-of-the-art broadband receivers. This dissertation also proposes a reconfigurable receiver for IoT-class radios that is tolerant to both close-in and far-out blockers. A scalable clock bootstrapping technique is introduced to enhance linearity while maintaining both power and cost efficiency. All designs are validated through prototypes fabricated in advanced 22-nm and 45-nm silicon-on-insulator (SOI) technologies. By addressing this long-standing challenge, this work paves the way for fully reconfigurable, interference-resilient radios for 5G and beyond.

Degree

thesis:*
Name thesis:degree_name
Doctoral
Department dc:contributor.department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Grantor dc:publisher
Massachusetts Institute of Technology
Year dc:date.issued
2025

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Araei, Soroush
Advisor dc:contributor.advisor
  • Reiskarimian, Negar

Rights

dc:rights
Statement dc:rights
  • In Copyright - Educational Use Permitted
  • Copyright retained by author(s)

Identifiers

dc:identifier.*
Handle dc:identifier.uri
https://hdl.handle.net/1721.1/164585
OAI identifier oai:identifier
oai:dspace.mit.edu:1721.1/164585

Chain of custody

source
Harvested from
MIT
Base URL
dspace.mit.edu/oai/request
Last updated
2026-07-22
Source record
OAI-PMH GetRecord
related terms
citation

Araei, Soroush. Reconfigurable and Interference-Tolerant Receivers for Next Generation Wireless Systems. Massachusetts Institute of Technology, 2025. https://hdl.handle.net/1721.1/164585