Evaluating the Feasibility of Transaction Scheduling via Hardware Accelerators

As single-thread performance plateaus, modern systems increasingly rely on parallelism to scale throughput. Yet, efciently managing concurrency—particularly in transactional systems—remains a major bottleneck. This thesis explores the feasibility of accelerating transaction scheduling via hardware, leveraging FPGAs to ofoad scheduling logic from the CPU. We revisit Puppetmaster, a hardware transaction scheduler, and present a redesigned architecture emphasizing deployability, modularity, and evaluation. We implement both an optimized software baseline and a Bluespec-based hardware design, evaluating their performance across synthetic YCSB-style workloads with varying contention levels. Our hardware prototype demonstrates competitive throughput, achieving over 90% of peak throughput even under high-contention workloads. These results validate the potential of transaction scheduling as a target for hardware acceleration and highlight promising directions for future hybrid hardware-software concurrency-control systems.

Name thesis:degree_name

Master

Department dc:contributor.department

Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2025

Author dc:creator

• Chomphoochan, Thanadol

Advisor dc:contributor.advisor

• Chlipala, Adam

Statement dc:rights

• Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0)
• Copyright retained by author(s)

Licence dc:rights.uri

• https://creativecommons.org/licenses/by-nc-sa/4.0/

Handle dc:identifier.uri

https://hdl.handle.net/1721.1/162741

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/162741