Energy Efficient Real-time Operating Systems on Chip

Autonomous micro-robots are crucial for several tasks, such as search and rescue, noknowledge mapping, and navigation. Without an external power connection, these robots are constrained by their on-platform energy capacity. The power consumption of actuation systems used in micro-robots is within the same magnitude of the power consumption of the compute system. Thus, the remaining factor for enabling these micro-robots is associated with the design of energy-efficient compute systems. Energy usage of compute systems is typically dominated by memory operations, which previous efforts have attempted to mitigate with memory efficient software and hardware. These efforts are enabled with the software/hardware interface, which is implemented as an Operating System (OS). However, Operating Systems for energy-efficient platforms have not been fully explored. Current approaches utilize full general-purpose Operating Systems such as Linux, which can incur large memory and compute overhead penalties. These overheads not only consume the typically limited memory resources of energy-efficient systems, but also increase the number of memory accesses and CPU cycles, both of which are significant contributors to energy consumption. To address these concerns, we propose the design of a computational and memory efficient Real-time Operating System (RTOS). Our RTOS is designed to minimize both memory footprint and compute cycle overhead. It achieves this primarily through direct physical memory access, cycle-efficient task scheduling, and minimal runtime services to avoid unnecessary processing. Additionally, the modular RTOS kernel includes only the components required by an application in the final binary, reducing code size and memory usage without compromising functionality. The design enables the utilization of energy-efficient hardware accelerators and software, allowing for execution of robotics workloads with minimal memory and cycle overhead. When comparing robotics algorithms implemented on our proposed RTOS and baseline OSes, our design was able to achieve a 99% reduction in memory footprint. Additionally, it achieved up to a 47% increase in throughput. Thus, our design demonstrates a direct reduction in memory and CPU cycle overhead, which in turn lowers total system memory and energy consumption. The proposed design was demonstrated and verified on a resource constrained system-on-chip on the AMD Virtex Ultrascale+ VCU118 FPGA.

Name thesis:degree_name

Master

Department dc:contributor.department

Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2025

Author dc:creator

• Kang, Ezra H.

Advisor dc:contributor.advisor

• Sze, Vivienne

Statement dc:rights

• Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0)
• Copyright retained by author(s)

Licence dc:rights.uri

• https://creativecommons.org/licenses/by-nc-nd/4.0/

Handle dc:identifier.uri

https://hdl.handle.net/1721.1/162705

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/162705