A Technology Platform for Enabling Next-Generation Vacuum Electronic Devices Based on Silicon Field Emitter Arrays

As the demand for electronics with better performance and increased functionality continues to escalate, researchers are finding it more and more difficult to surpass the limitations of conventional transistors due to electron transport in solid-state. Nanoscale vacuum-channel transistors, in which the electron transport channel is vacuum instead of solid-state, offer a potential alternative device architecture beyond device scaling. Due to their ballistic transport and higher breakdown field, nanoscale vacuum-channel transistors are expected to show better performance in a wide variety of high-frequency, high-power, or harsh environment applications. Silicon field emitter arrays (FEAs) are a proven and mature technology that can be implemented as vacuum transistors, and they could also be used in vacuum integrated circuits. Many of the challenges regarding uniformity, reliability, and lifetime have been addressed in this technology. However, the scalability of the emission current remains a challenge. In this work, we develop a layout-independent fabrication process for silicon FEAs that improves the scalability of emission current with array size. The fabrication process begins by first fabricating field emitters everywhere across the wafer and then selectively etching field emitters to form individual arrays. Using this process, we present for the first time silicon FEAs with array sizes ranging from 1 μm2 to 1 mm2, and we obtain emission current ranging from 1 nA to 1 mA, which represents a range of six orders of magnitude. In order to facilitate design of future vacuum integrated circuits, we develop a circuit model for silicon FEAs based on measurements of the transfer and output characteristics. The circuit model is used to demonstrate a proof-of-concept inverter based on a silicon FEA and pull-up resistor that could potentially be fabricated as a vacuum integrated circuit. Lastly, we characterize and model the statistical variation in emission current to determine if it is feasible to build vacuum integrated circuits using the layout-independent fabrication process presented in this work.

Name thesis:degree_name

Doctoral

Department dc:contributor.department

Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2024

Author dc:creator

• Karaulac, Nedeljko

Advisor dc:contributor.advisor

• Akinwande, Akintunde I.

Statement dc:rights

• In Copyright - Educational Use Permitted
• Copyright retained by author(s)

Licence dc:rights.uri

• https://rightsstatements.org/page/InC-EDU/1.0/

Handle dc:identifier.uri

https://hdl.handle.net/1721.1/158519

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/158519