{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/156286"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/156286","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"Device Stack Optimization for Protonic Non-Volatile Programmable Resistors","abstract":"Analog computing could alleviate computational bottlenecks in digital deep learning systems by utilizing local information processing through the physical properties of devices, such as electrochemical ion-intercalation in three-terminal devices where channel resistance is modulated by ionic exchange via an electrolyte. Previous work has demonstrated such ionic programmable resistors featuring WO₃ as the channel, phosphorous-doped SiO₂ (PSG) as the electrolyte, Pd as the gate reservoir, and protons as the ions. This thesis aimed to optimize the device stack in four directions and demonstrated a symmetric WO₃-PSG-WO₃ structure in a CMOS-compatible process, with the help of circular transfer length model (CTLM), which efficiently examines the resistance properties of WO₃. We have explored: (a) device protonation as part of the fabrication process, (b) encapsulation preventing proton depletion during device fabrication and operation, (c) contact metal optimization to replace gold with a CMOS-compatible material, (d) PSG evaluation vehicle for device performance optimization. The symmetric device combining all the stack optimizations features non-volatile and repeatable conductance modulation with voltage pulses.","abstract_html":"Analog computing could alleviate computational bottlenecks in digital deep learning systems by utilizing local information processing through the physical properties of devices, such as electrochemical ion-intercalation in three-terminal devices where channel resistance is modulated by ionic exchange via an electrolyte. Previous work has demonstrated such ionic programmable resistors featuring WO₃ as the channel, phosphorous-doped SiO₂ (PSG) as the electrolyte, Pd as the gate reservoir, and protons as the ions. This thesis aimed to optimize the device stack in four directions and demonstrated a symmetric WO₃-PSG-WO₃ structure in a CMOS-compatible process, with the help of circular transfer length model (CTLM), which efficiently examines the resistance properties of WO₃. We have explored: (a) device protonation as part of the fabrication process, (b) encapsulation preventing proton depletion during device fabrication and operation, (c) contact metal optimization to replace gold with a CMOS-compatible material, (d) PSG evaluation vehicle for device performance optimization. The symmetric device combining all the stack optimizations features non-volatile and repeatable conductance modulation with voltage pulses.","abstract_has_math":false,"creators":["Shen, Dingyu"],"institution":"Massachusetts Institute of Technology","degree_name":"Master","degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science","school":null,"contributors":[],"advisors":["del Alamo, Jesús A."],"committee_chairs":[],"committee_members":[],"year":2024,"date_issued":"2024-05","date_published":"2024-05","updated_at":"2026-07-22T22:22:10Z","subjects":[],"languages":[],"rights":["In Copyright - Educational Use Permitted","Copyright retained by author(s)"],"rights_urls":["https://rightsstatements.org/page/InC-EDU/1.0/"],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/1721.1/156286","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["del Alamo, Jesús A."]},{"key":"dc:contributor.department","label":"Department","values":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science"]},{"key":"dc:creator","label":"Author","values":["Shen, Dingyu"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2024-08-21T18:54:04Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2024-08-21T18:54:04Z"]},{"key":"dc:date.issued","label":"Date","values":["2024-05"]},{"key":"dc:publisher","label":"Institution","values":["Massachusetts Institute of Technology"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master","Master of Science in Electrical Engineering and Computer Science"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:rights","label":"Dc Rights","values":["In Copyright - Educational Use Permitted","Copyright retained by author(s)"]},{"key":"dc:rights.uri","label":"Rights URI","values":["https://rightsstatements.org/page/InC-EDU/1.0/"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["https://hdl.handle.net/1721.1/156286"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["Analog computing could alleviate computational bottlenecks in digital deep learning systems by utilizing local information processing through the physical properties of devices, such as electrochemical ion-intercalation in three-terminal devices where channel resistance is modulated by ionic exchange via an electrolyte. Previous work has demonstrated such ionic programmable resistors featuring WO₃ as the channel, phosphorous-doped SiO₂ (PSG) as the electrolyte, Pd as the gate reservoir, and protons as the ions. This thesis aimed to optimize the device stack in four directions and demonstrated a symmetric WO₃-PSG-WO₃ structure in a CMOS-compatible process, with the help of circular transfer length model (CTLM), which efficiently examines the resistance properties of WO₃. We have explored: (a) device protonation as part of the fabrication process, (b) encapsulation preventing proton depletion during device fabrication and operation, (c) contact metal optimization to replace gold with a CMOS-compatible material, (d) PSG evaluation vehicle for device performance optimization. The symmetric device combining all the stack optimizations features non-volatile and repeatable conductance modulation with voltage pulses."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["S.M."]},{"key":"dc:title","label":"Title","values":["Device Stack Optimization for Protonic Non-Volatile Programmable Resistors"]}]}],"canonical_facts":{"dc:contributor.advisor":["del Alamo, Jesús A."],"dc:contributor.department":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science"],"dc:creator":["Shen, Dingyu"],"dc:date.accessioned":["2024-08-21T18:54:04Z"],"dc:date.available":["2024-08-21T18:54:04Z"],"dc:date.issued":["2024-05"],"dc:description.abstract":["Analog computing could alleviate computational bottlenecks in digital deep learning systems by utilizing local information processing through the physical properties of devices, such as electrochemical ion-intercalation in three-terminal devices where channel resistance is modulated by ionic exchange via an electrolyte. Previous work has demonstrated such ionic programmable resistors featuring WO₃ as the channel, phosphorous-doped SiO₂ (PSG) as the electrolyte, Pd as the gate reservoir, and protons as the ions. This thesis aimed to optimize the device stack in four directions and demonstrated a symmetric WO₃-PSG-WO₃ structure in a CMOS-compatible process, with the help of circular transfer length model (CTLM), which efficiently examines the resistance properties of WO₃. We have explored: (a) device protonation as part of the fabrication process, (b) encapsulation preventing proton depletion during device fabrication and operation, (c) contact metal optimization to replace gold with a CMOS-compatible material, (d) PSG evaluation vehicle for device performance optimization. The symmetric device combining all the stack optimizations features non-volatile and repeatable conductance modulation with voltage pulses."],"dc:description.degree":["S.M."],"dc:identifier.uri":["https://hdl.handle.net/1721.1/156286"],"dc:publisher":["Massachusetts Institute of Technology"],"dc:rights":["In Copyright - Educational Use Permitted","Copyright retained by author(s)"],"dc:rights.uri":["https://rightsstatements.org/page/InC-EDU/1.0/"],"dc:title":["Device Stack Optimization for Protonic Non-Volatile Programmable Resistors"],"dc:type":["Thesis"],"thesis:degree_name":["Master","Master of Science in Electrical Engineering and Computer Science"]},"updated_at":"2026-07-22T22:22:10Z"}