{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/153859"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/153859","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"Microarchitecture Categorization and Pre-RTL Analytical Modeling for Sparse Tensor Accelerators","abstract":"Specialized microarchitectures for exploiting sparsity have been critical to the design of sparse tensor accelerators. Sparseloop introduced the Sparse Acceleration Fea­ture (SAF) abstraction, which unifies prior work on sparse tensor accelerators into a taxonomy of sparsity optimizations. Sparseloop succeeds at analytical pre-RTL modeling of architecture-level metrics for sparse tensor accelerators, accurately capturing the beneficial impact of SAFs on overall design cost. However, Sparseloop lacks cost models for microarchitectural primitives and design topologies required for implementing SAFs (referred to in this work as \"SAF microarchitectures\".) Analysis of prior works shows that SAF microarchitectures may or may not con­stitute a significant overhead, depending on the particular design; thus it is desirable to have pre-RTL models which help anticipate SAF microarchitecture overheads. Building on the Sparseloop SAF abstraction, this work1 attempts to synthesize a number of prior works into a concise, unified, and effective framework for doing research on SAF microarchitectures. This overall framework comprises (1) a concep­tual framework which facilitates concise description and design-space exploration for SAF microarchitectures, (2) a software framework for compiling Sparseloop-style SAF descriptions into microarchitecture designs and analytical models, and (3) a compo­nent library including specific SAF microarchitecture subcomponent designs as well as RTL to support implementation.","abstract_html":"Specialized microarchitectures for exploiting sparsity have been critical to the design of sparse tensor accelerators. Sparseloop introduced the Sparse Acceleration Fea­ture (SAF) abstraction, which unifies prior work on sparse tensor accelerators into a taxonomy of sparsity optimizations. Sparseloop succeeds at analytical pre-RTL modeling of architecture-level metrics for sparse tensor accelerators, accurately capturing the beneficial impact of SAFs on overall design cost. However, Sparseloop lacks cost models for microarchitectural primitives and design topologies required for implementing SAFs (referred to in this work as "SAF microarchitectures".) Analysis of prior works shows that SAF microarchitectures may or may not con­stitute a significant overhead, depending on the particular design; thus it is desirable to have pre-RTL models which help anticipate SAF microarchitecture overheads. Building on the Sparseloop SAF abstraction, this work1 attempts to synthesize a number of prior works into a concise, unified, and effective framework for doing research on SAF microarchitectures. This overall framework comprises (1) a concep­tual framework which facilitates concise description and design-space exploration for SAF microarchitectures, (2) a software framework for compiling Sparseloop-style SAF descriptions into microarchitecture designs and analytical models, and (3) a compo­nent library including specific SAF microarchitecture subcomponent designs as well as RTL to support implementation.","abstract_has_math":false,"creators":["Feldman, Andrew"],"institution":"Massachusetts Institute of Technology","degree_name":"Master","degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. 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Sparseloop introduced the Sparse Acceleration Fea­ture (SAF) abstraction, which unifies prior work on sparse tensor accelerators into a taxonomy of sparsity optimizations. Sparseloop succeeds at analytical pre-RTL modeling of architecture-level metrics for sparse tensor accelerators, accurately capturing the beneficial impact of SAFs on overall design cost. However, Sparseloop lacks cost models for microarchitectural primitives and design topologies required for implementing SAFs (referred to in this work as \"SAF microarchitectures\".) Analysis of prior works shows that SAF microarchitectures may or may not con­stitute a significant overhead, depending on the particular design; thus it is desirable to have pre-RTL models which help anticipate SAF microarchitecture overheads. Building on the Sparseloop SAF abstraction, this work1 attempts to synthesize a number of prior works into a concise, unified, and effective framework for doing research on SAF microarchitectures. This overall framework comprises (1) a concep­tual framework which facilitates concise description and design-space exploration for SAF microarchitectures, (2) a software framework for compiling Sparseloop-style SAF descriptions into microarchitecture designs and analytical models, and (3) a compo­nent library including specific SAF microarchitecture subcomponent designs as well as RTL to support implementation."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["M.Eng."]},{"key":"dc:title","label":"Title","values":["Microarchitecture Categorization and Pre-RTL Analytical Modeling for Sparse Tensor Accelerators"]}]}],"canonical_facts":{"dc:contributor.advisor":["Sze, Vivienne","Erner, Joel"],"dc:contributor.department":["Massachusetts Institute of Technology. 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Analysis of prior works shows that SAF microarchitectures may or may not con­stitute a significant overhead, depending on the particular design; thus it is desirable to have pre-RTL models which help anticipate SAF microarchitecture overheads. Building on the Sparseloop SAF abstraction, this work1 attempts to synthesize a number of prior works into a concise, unified, and effective framework for doing research on SAF microarchitectures. This overall framework comprises (1) a concep­tual framework which facilitates concise description and design-space exploration for SAF microarchitectures, (2) a software framework for compiling Sparseloop-style SAF descriptions into microarchitecture designs and analytical models, and (3) a compo­nent library including specific SAF microarchitecture subcomponent designs as well as RTL to support implementation."],"dc:description.degree":["M.Eng."],"dc:identifier.uri":["https://hdl.handle.net/1721.1/153859"],"dc:publisher":["Massachusetts Institute of Technology"],"dc:rights":["In Copyright - Educational Use Permitted","Copyright retained by author(s)"],"dc:rights.uri":["https://rightsstatements.org/page/InC-EDU/1.0/"],"dc:title":["Microarchitecture Categorization and Pre-RTL Analytical Modeling for Sparse Tensor Accelerators"],"dc:type":["Thesis"],"thesis:degree_name":["Master","Master of Engineering in Electrical Engineering and Computer Science"]},"updated_at":"2026-07-22T22:22:06Z"}