{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/151650"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/151650","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"A Continuous-Time Pipeline ADC with Reduced Sensitivity to Clock Jitter","abstract":"With the advent of the fifth-generation (5G) standard for cellular networks, direct RF receivers are becoming popular in applications such as cellular base stations. Such systems require analog-to-digital converters (ADC) with a high dynamic range over a large digitization bandwidth (> 500 MHz). For high-speed high-resolution ADCs with an upfront sampler, the clock jitter poses a fundamental bottleneck for the maximum achievable signal-to-noise ratio (SNR). In applications requiring 10-12 bit resolution for 1 GHz digitization bandwidth, the clock jitter values must be no more than a few tens of femtoseconds. This poses significant design challenges for the clock generator. The continuous-time (CT) pipeline ADC is an emerging architecture that combines the benefits of a discrete-time pipeline ADC and a continuous-time ∆Σ ADC architecture. In this thesis, we explore the clock jitter sensitivity of the CT pipeline ADC. We derive the SNR limitations in a CT pipeline ADC and propose a new CT pipeline ADC design with improved tolerance to clock jitter. We also present a design methodology for the delay line and propose a novel inductor-less delay line that provides a good amplitude and phase matching between the stage 1 signal path and the sub-ADC-DAC path from DC to 1.6 GHz to minimize the signal leakage in the first stage residue. A prototype ADC was fabricated in a 16-nm FinFET process. The ADC achieves 61.7/60.8dB (low/high frequency) SNR over 1-GHz bandwidth. The active area is 0.77mm² and the ADC consumes 240mW. The Schreier figure-of-merit (FOMS) is 157.9dB which is amongst the best in comparison to other state-of-the-art continuous-time ADCs with digitization bandwidth greater than 500MHz.","abstract_html":"With the advent of the fifth-generation (5G) standard for cellular networks, direct RF receivers are becoming popular in applications such as cellular base stations. Such systems require analog-to-digital converters (ADC) with a high dynamic range over a large digitization bandwidth (> 500 MHz). For high-speed high-resolution ADCs with an upfront sampler, the clock jitter poses a fundamental bottleneck for the maximum achievable signal-to-noise ratio (SNR). In applications requiring 10-12 bit resolution for 1 GHz digitization bandwidth, the clock jitter values must be no more than a few tens of femtoseconds. This poses significant design challenges for the clock generator. The continuous-time (CT) pipeline ADC is an emerging architecture that combines the benefits of a discrete-time pipeline ADC and a continuous-time ∆Σ ADC architecture. In this thesis, we explore the clock jitter sensitivity of the CT pipeline ADC. We derive the SNR limitations in a CT pipeline ADC and propose a new CT pipeline ADC design with improved tolerance to clock jitter. We also present a design methodology for the delay line and propose a novel inductor-less delay line that provides a good amplitude and phase matching between the stage 1 signal path and the sub-ADC-DAC path from DC to 1.6 GHz to minimize the signal leakage in the first stage residue. A prototype ADC was fabricated in a 16-nm FinFET process. The ADC achieves 61.7/60.8dB (low/high frequency) SNR over 1-GHz bandwidth. The active area is 0.77mm² and the ADC consumes 240mW. The Schreier figure-of-merit (FOMS) is 157.9dB which is amongst the best in comparison to other state-of-the-art continuous-time ADCs with digitization bandwidth greater than 500MHz.","abstract_has_math":false,"creators":["Mittal, Rishabh"],"institution":"Massachusetts Institute of Technology","degree_name":"Doctoral","degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science","school":null,"contributors":[],"advisors":["Lee, Hae-Seung","Chandrakasan, Anantha P."],"committee_chairs":[],"committee_members":[],"year":2023,"date_issued":"2023-06","date_published":"2023-06","updated_at":"2026-07-22T22:21:55Z","subjects":[],"languages":[],"rights":["In Copyright - Educational Use Permitted","Copyright retained by author(s)"],"rights_urls":["https://rightsstatements.org/page/InC-EDU/1.0/"],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/1721.1/151650","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Lee, Hae-Seung","Chandrakasan, Anantha P."]},{"key":"dc:contributor.department","label":"Department","values":["Massachusetts Institute of Technology. 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Such systems require analog-to-digital converters (ADC) with a high dynamic range over a large digitization bandwidth (> 500 MHz). For high-speed high-resolution ADCs with an upfront sampler, the clock jitter poses a fundamental bottleneck for the maximum achievable signal-to-noise ratio (SNR). In applications requiring 10-12 bit resolution for 1 GHz digitization bandwidth, the clock jitter values must be no more than a few tens of femtoseconds. This poses significant design challenges for the clock generator. The continuous-time (CT) pipeline ADC is an emerging architecture that combines the benefits of a discrete-time pipeline ADC and a continuous-time ∆Σ ADC architecture. In this thesis, we explore the clock jitter sensitivity of the CT pipeline ADC. We derive the SNR limitations in a CT pipeline ADC and propose a new CT pipeline ADC design with improved tolerance to clock jitter. We also present a design methodology for the delay line and propose a novel inductor-less delay line that provides a good amplitude and phase matching between the stage 1 signal path and the sub-ADC-DAC path from DC to 1.6 GHz to minimize the signal leakage in the first stage residue. A prototype ADC was fabricated in a 16-nm FinFET process. The ADC achieves 61.7/60.8dB (low/high frequency) SNR over 1-GHz bandwidth. The active area is 0.77mm² and the ADC consumes 240mW. The Schreier figure-of-merit (FOMS) is 157.9dB which is amongst the best in comparison to other state-of-the-art continuous-time ADCs with digitization bandwidth greater than 500MHz."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["Ph.D."]},{"key":"dc:title","label":"Title","values":["A Continuous-Time Pipeline ADC with Reduced Sensitivity to Clock Jitter"]}]}],"canonical_facts":{"dc:contributor.advisor":["Lee, Hae-Seung","Chandrakasan, Anantha P."],"dc:contributor.department":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science"],"dc:creator":["Mittal, Rishabh"],"dc:date.accessioned":["2023-07-31T19:56:06Z"],"dc:date.available":["2023-07-31T19:56:06Z"],"dc:date.issued":["2023-06"],"dc:description.abstract":["With the advent of the fifth-generation (5G) standard for cellular networks, direct RF receivers are becoming popular in applications such as cellular base stations. Such systems require analog-to-digital converters (ADC) with a high dynamic range over a large digitization bandwidth (> 500 MHz). For high-speed high-resolution ADCs with an upfront sampler, the clock jitter poses a fundamental bottleneck for the maximum achievable signal-to-noise ratio (SNR). In applications requiring 10-12 bit resolution for 1 GHz digitization bandwidth, the clock jitter values must be no more than a few tens of femtoseconds. This poses significant design challenges for the clock generator. The continuous-time (CT) pipeline ADC is an emerging architecture that combines the benefits of a discrete-time pipeline ADC and a continuous-time ∆Σ ADC architecture. In this thesis, we explore the clock jitter sensitivity of the CT pipeline ADC. We derive the SNR limitations in a CT pipeline ADC and propose a new CT pipeline ADC design with improved tolerance to clock jitter. We also present a design methodology for the delay line and propose a novel inductor-less delay line that provides a good amplitude and phase matching between the stage 1 signal path and the sub-ADC-DAC path from DC to 1.6 GHz to minimize the signal leakage in the first stage residue. A prototype ADC was fabricated in a 16-nm FinFET process. The ADC achieves 61.7/60.8dB (low/high frequency) SNR over 1-GHz bandwidth. The active area is 0.77mm² and the ADC consumes 240mW. The Schreier figure-of-merit (FOMS) is 157.9dB which is amongst the best in comparison to other state-of-the-art continuous-time ADCs with digitization bandwidth greater than 500MHz."],"dc:description.degree":["Ph.D."],"dc:identifier.uri":["https://hdl.handle.net/1721.1/151650"],"dc:publisher":["Massachusetts Institute of Technology"],"dc:rights":["In Copyright - Educational Use Permitted","Copyright retained by author(s)"],"dc:rights.uri":["https://rightsstatements.org/page/InC-EDU/1.0/"],"dc:title":["A Continuous-Time Pipeline ADC with Reduced Sensitivity to Clock Jitter"],"dc:type":["Thesis"],"thesis:degree_name":["Doctoral","Doctor of Philosophy"]},"updated_at":"2026-07-22T22:21:55Z"}