{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/147361"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/147361","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"GaN Electronics for High-Temperature Applications","abstract":"Gallium nitride is a promising candidate for harsh environment electronics, thanks to its excellent material properties, which have given rise to high-performance (room temperature) transistors for RF, power, MEMS, and mixed-signal applications. Previous works on high-temperature (HT) electronics have been typically limited to two aspects, namely, the high-temperature robustness of discrete transistors and basic circuit building blocks, which are mainly combinational logic. While these studies offer a strong indication of the potential of GaN transistor technology for HT applications, the development of HT (500 °C) GaN-ICs is still at its early stage due to the low degree of complexity and integration demonstrated so far. Major challenges in the realization of GaN HT-robust sequential logic circuits or more complex systems is the lack of a scalable technology. This thesis aims to advance the integration technology of GaN HT electronics by demonstrating a comprehensive HT (500°C) enhancement-mode (E-mode) GaN-on-Si technology from device to circuit perspectives: (1) a scalable device technology based on p-GaN-gate AlGaN/GaN HEMTs with high uniformity, which is optimized for HT operation and demonstrated to offer robust performance at least up to 500 °C with the help of in-house developed packaging technology and characterization platform, (2) compact modeling of monolithically integrated enhancement/depletion-mode HEMTs up to 500 °C HEMTs, (3) robustness-driven circuit design based on GaN technology, (4) demonstration of GaN-based combinational and sequential building blocks including inverter, NAND, NOR, ring oscillators, ROM, SRAM, D Latch, D Flip-Flop operational up to 500 °C.","abstract_html":"Gallium nitride is a promising candidate for harsh environment electronics, thanks to its excellent material properties, which have given rise to high-performance (room temperature) transistors for RF, power, MEMS, and mixed-signal applications. Previous works on high-temperature (HT) electronics have been typically limited to two aspects, namely, the high-temperature robustness of discrete transistors and basic circuit building blocks, which are mainly combinational logic. While these studies offer a strong indication of the potential of GaN transistor technology for HT applications, the development of HT (500 °C) GaN-ICs is still at its early stage due to the low degree of complexity and integration demonstrated so far. Major challenges in the realization of GaN HT-robust sequential logic circuits or more complex systems is the lack of a scalable technology. This thesis aims to advance the integration technology of GaN HT electronics by demonstrating a comprehensive HT (500°C) enhancement-mode (E-mode) GaN-on-Si technology from device to circuit perspectives: (1) a scalable device technology based on p-GaN-gate AlGaN/GaN HEMTs with high uniformity, which is optimized for HT operation and demonstrated to offer robust performance at least up to 500 °C with the help of in-house developed packaging technology and characterization platform, (2) compact modeling of monolithically integrated enhancement/depletion-mode HEMTs up to 500 °C HEMTs, (3) robustness-driven circuit design based on GaN technology, (4) demonstration of GaN-based combinational and sequential building blocks including inverter, NAND, NOR, ring oscillators, ROM, SRAM, D Latch, D Flip-Flop operational up to 500 °C.","abstract_has_math":false,"creators":["Yuan, Mengyang"],"institution":"Massachusetts Institute of Technology","degree_name":"Doctoral","degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science","school":null,"contributors":[],"advisors":["Palacios, Tomás"],"committee_chairs":[],"committee_members":[],"year":2022,"date_issued":"2022-09","date_published":"2022-09","updated_at":"2026-07-22T22:22:03Z","subjects":[],"languages":[],"rights":["In Copyright - Educational Use Permitted","Copyright MIT"],"rights_urls":["http://rightsstatements.org/page/InC-EDU/1.0/"],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/1721.1/147361","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Palacios, Tomás"]},{"key":"dc:contributor.department","label":"Department","values":["Massachusetts Institute of Technology. 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Previous works on high-temperature (HT) electronics have been typically limited to two aspects, namely, the high-temperature robustness of discrete transistors and basic circuit building blocks, which are mainly combinational logic. While these studies offer a strong indication of the potential of GaN transistor technology for HT applications, the development of HT (500 °C) GaN-ICs is still at its early stage due to the low degree of complexity and integration demonstrated so far. Major challenges in the realization of GaN HT-robust sequential logic circuits or more complex systems is the lack of a scalable technology. This thesis aims to advance the integration technology of GaN HT electronics by demonstrating a comprehensive HT (500°C) enhancement-mode (E-mode) GaN-on-Si technology from device to circuit perspectives: (1) a scalable device technology based on p-GaN-gate AlGaN/GaN HEMTs with high uniformity, which is optimized for HT operation and demonstrated to offer robust performance at least up to 500 °C with the help of in-house developed packaging technology and characterization platform, (2) compact modeling of monolithically integrated enhancement/depletion-mode HEMTs up to 500 °C HEMTs, (3) robustness-driven circuit design based on GaN technology, (4) demonstration of GaN-based combinational and sequential building blocks including inverter, NAND, NOR, ring oscillators, ROM, SRAM, D Latch, D Flip-Flop operational up to 500 °C."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["Ph.D."]},{"key":"dc:title","label":"Title","values":["GaN Electronics for High-Temperature Applications"]}]}],"canonical_facts":{"dc:contributor.advisor":["Palacios, Tomás"],"dc:contributor.department":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science"],"dc:creator":["Yuan, Mengyang"],"dc:date.accessioned":["2023-01-19T18:48:09Z"],"dc:date.available":["2023-01-19T18:48:09Z"],"dc:date.issued":["2022-09"],"dc:description.abstract":["Gallium nitride is a promising candidate for harsh environment electronics, thanks to its excellent material properties, which have given rise to high-performance (room temperature) transistors for RF, power, MEMS, and mixed-signal applications. Previous works on high-temperature (HT) electronics have been typically limited to two aspects, namely, the high-temperature robustness of discrete transistors and basic circuit building blocks, which are mainly combinational logic. While these studies offer a strong indication of the potential of GaN transistor technology for HT applications, the development of HT (500 °C) GaN-ICs is still at its early stage due to the low degree of complexity and integration demonstrated so far. Major challenges in the realization of GaN HT-robust sequential logic circuits or more complex systems is the lack of a scalable technology. This thesis aims to advance the integration technology of GaN HT electronics by demonstrating a comprehensive HT (500°C) enhancement-mode (E-mode) GaN-on-Si technology from device to circuit perspectives: (1) a scalable device technology based on p-GaN-gate AlGaN/GaN HEMTs with high uniformity, which is optimized for HT operation and demonstrated to offer robust performance at least up to 500 °C with the help of in-house developed packaging technology and characterization platform, (2) compact modeling of monolithically integrated enhancement/depletion-mode HEMTs up to 500 °C HEMTs, (3) robustness-driven circuit design based on GaN technology, (4) demonstration of GaN-based combinational and sequential building blocks including inverter, NAND, NOR, ring oscillators, ROM, SRAM, D Latch, D Flip-Flop operational up to 500 °C."],"dc:description.degree":["Ph.D."],"dc:identifier.uri":["https://hdl.handle.net/1721.1/147361"],"dc:publisher":["Massachusetts Institute of Technology"],"dc:rights":["In Copyright - Educational Use Permitted","Copyright MIT"],"dc:rights.uri":["http://rightsstatements.org/page/InC-EDU/1.0/"],"dc:title":["GaN Electronics for High-Temperature Applications"],"dc:type":["Thesis"],"thesis:degree_name":["Doctoral","Doctor of Philosophy"]},"updated_at":"2026-07-22T22:22:03Z"}