Optimizing Vector Instruction Selection for Digital Signal Processing

Digital signal processing applications benefit from fast implementations of vectorized inner kernels. Existing compilers rely on brittle pattern-matching or search-based methods with poor scalability for vector instruction selection – techniques which are limited by a reliance on the syntax of the input code. These techniques struggle to utilize the efficient fused instructions that exist on modern hardware. This thesis extends the Rake synthesis-based optimizing compiler to target the ARM Neon ISA via the design of a high-level intermediate representation for vector computation, with each component of the IR unifying multiple concrete instructions for the target ISA. This technique relies on the semantics of the input code, rather than the syntax alone, allowing for powerful equivalent rewrites that existing compilers are currently incapable of performing. On 11 real-world benchmarks, our system achieves up to a 65% faster runtime (geometric mean of 12%) than the Halide and LLVM vector instruction selectors that have been developed over the past decade.

Name thesis:degree_name

Master

Department dc:contributor.department

Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2022

Author dc:creator

• Root, Alexander James

Advisors dc:contributor.advisor

• Ragan-Kelley, Jonathan
• Adams, Andrew

Statement dc:rights

• In Copyright - Educational Use Permitted
• Copyright MIT

Licence dc:rights.uri

• http://rightsstatements.org/page/InC-EDU/1.0/

Handle dc:identifier.uri

https://hdl.handle.net/1721.1/144935

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/144935