Digital Control for Dynamic Efficiency Optimization in Switching Regulators

Dynamic efficiency optimization leverages opportunities to minimize power loss and adaptively optimize switching regulator efficiency as the operating conditions change. This thesis details the development of an optimization system that dynamically optimizes the efficiency of a targeted converter. The optimization system is designed to be compatible and easily integrated with an existing monolithic converter to serve as a proof of concept for dynamic efficiency optimization. The monolithic converter targeted in this thesis is a next generation Analog Devices monolithic buck converter with telemetry accessible via the PMBus interface. A loss model of the targeted converter is derived from its specific topology and implementation. The loss model and prior works are used to identify possible means or opportunities for the optimization system to dynamically trade off losses to minimize the converters total loss and maximize its efficiency as its operating conditions change. The tradeoff opportunities, the prior works and the desire for compatibility with an already existing converter guide the development of the optimization system in this thesis. The proposed dynamic efficiency optimization system includes the modification of existing circuitry as well as the introduction of additional circuitry in the converter to enable the loss tradeoff, a digital algorithm to optimize the loss tradeoff and a method of estimating converter efficiency, which is used to inform the algorithms decision making. The potentially adverse thermal and control implications of the optimization on the targeted converter are also addressed with circuit modifications verified on the block level with transistor level simulations. The functionality of the entire system is verified with digital simulation that employs real number modeling (RNM) of the analog blocks, which enables rapid top level or functional simulation of mixed signal designs with both analog and digital blocks. The optimization systems efficacy will be experimentally determined by assembling the targeted monolithic converter modified for dynamic efficiency optimization with an external FPGA that implements the optimization algorithm on an evaluation board and measuring the dynamically optimized efficiency of the targeted converter. The process described in this thesis to implement dynamic efficiency optimization can be generally applied to other targeted converters.

Name thesis:degree_name

Master

Department dc:contributor.department

Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2022

Author dc:creator

• Cheng, Lok Hin

Advisors dc:contributor.advisor

• Bernardinis, Gabriele
• Perreault, David J.

Statement dc:rights

• In Copyright - Educational Use Permitted
• Copyright MIT

Licence dc:rights.uri

• http://rightsstatements.org/page/InC-EDU/1.0/

Handle dc:identifier.uri

https://hdl.handle.net/1721.1/143329

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/143329