Design of a Precision, Very Low 1/f Noise, Low Power, Rail-Rail I/O, Integrated Bi-CMOS Operational Amplifier

The detailed design of a precision, very low 1/𝑓 noise, 100𝜇A, 30V, rail to rail input and output, integrated Bi-CMOS operational amplifier is presented. Necessity for such an amplifier in the current technological space is examined. Specific attention is given to the novel design of a stable current source requiring no more than approximately 50mV of overhead, for use with a very low noise native NMOS differential input pair. An improved technique for analyzing MOSFET 1/𝑓 noise in modern simulation environments is explored. Special consideration is given to the usage of native NMOS devices as the primary input pair, which are required in order to meet the low noise and zero input bias current requirements simultaneously. Detailed descriptions of key amplifier stages are given; rail to rail input, folded cascode, Monticelli rail to rail output, and Miller compensation. Finally, amplifier transient, spectral, and noise results are presented and discussed.

Name thesis:degree_name

Master

Department dc:contributor.department

Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2022

Author dc:creator

• Chavez, Rhian Austin

Advisors dc:contributor.advisor

• Bourque, Lance
• Han, Ruonan

Statement dc:rights

• In Copyright - Educational Use Permitted
• Copyright MIT

Licence dc:rights.uri

• http://rightsstatements.org/page/InC-EDU/1.0/

Handle dc:identifier.uri

https://hdl.handle.net/1721.1/143308

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/143308