VeGen: A Vectorizer Generator for SIMD and Beyond

Vector instructions are ubiquitous in modern processors. Traditional compiler auto-vectorization techniques have focused on targeting single instruction multiple data (SIMD) instructions. However, these auto-vectorization techniques are not sufficiently powerful to model non-SIMD vector instructions, which can accelerate applications in domains such as image processing, digital signal processing, and machine learning. To target non-SIMD instruction, compiler developers have resorted to complicated, ad hoc peephole optimizations, expending significant development time while still coming up short. As vector instruction sets continue to rapidly evolve, compilers cannot keep up with these new hardware capabilities. To facilitate the adaption of complex non-SIMD vector instructions, I propose a new model of vector parallelism that captures the semantics of these instructions and a new framework extracting this new model of vector parallelism automatically based on the formal semantics of the non-SIMD instructions.

Name thesis:degree_name

Master

Department dc:contributor.department

Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2021

Author dc:creator

• Chen, Yishen

Advisor dc:contributor.advisor

• Amarasinghe, Saman

Statement dc:rights

• In Copyright - Educational Use Permitted
• Copyright MIT

Licence dc:rights.uri

• http://rightsstatements.org/page/InC-EDU/1.0/

Handle dc:identifier.uri

https://hdl.handle.net/1721.1/140040

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/140040