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Massachusetts Institute of Technology

Efficient Algorithms, Protocols and Hardware Architectures for Next-Generation Cryptography in Embedded Systems

Abstract

dc:description.abstract

The Internet of Things (IoT) consists of an ever-growing network of wireless-connected electronic devices which are always collecting, processing and communicating data. While the IoT has inspired many new applications, these embedded devices have unique security challenges, thus making IoT security a major concern. Security architectures for IoT devices, both software and hardware, must be low-power and have low energy consumption, while still providing strong cryptographic guarantees and side-channel resilience. Network security protocols use a variety of cryptographic algorithms to achieve these goals. However, the associated computational complexity makes it extremely important to have low-power and energy-efficient embedded implementations of cryptography, especially public key algorithms. The research presented in this thesis demonstrates the design, implementation and experimental validation of efficient next-generation cryptography for embedded systems using software optimization, hardware acceleration and software-hardware co-design, along with side-channel countermeasures. Using circuit, architecture and algorithm techniques, efficient hardware-accelerated implementations of elliptic curve cryptography, pairing-based cryptography, lattice-based cryptography and other post-quantum cryptography algorithms are demonstrated with up to two orders of magnitude energy savings compared to state-of-the-art software and hardware. These configurable hardware accelerators are further coupled with a low-power micro-processor to provide the flexibility to implement a wide variety of security protocols, thus enabling strong and affordable security for energy-limited IoT nodes.

Degree

thesis:*
Name thesis:degree_name
Doctoral
Department dc:contributor.department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Grantor dc:publisher
Massachusetts Institute of Technology
Year dc:date.issued
2021

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Banerjee, Utsav
Advisor dc:contributor.advisor
  • Chandrakasan, Anantha P.

Rights

dc:rights
Statement dc:rights
  • In Copyright - Educational Use Permitted
  • Copyright MIT

Identifiers

dc:identifier.*
Handle dc:identifier.uri
https://hdl.handle.net/1721.1/139330
OAI identifier oai:identifier
oai:dspace.mit.edu:1721.1/139330

Chain of custody

source
Harvested from
MIT
Base URL
dspace.mit.edu/oai/request
Last updated
2026-07-22
Source record
OAI-PMH GetRecord
related terms
citation

Banerjee, Utsav. Efficient Algorithms, Protocols and Hardware Architectures for Next-Generation Cryptography in Embedded Systems. Massachusetts Institute of Technology, 2021. https://hdl.handle.net/1721.1/139330