Three-dimensional device and circuit architectures : new systems with new nanotechnologies

Physical scaling of silicon-based field-effect transistors (FETs) has been a major driving force to improve computing energy efficiency (quantified by the energy-delay product, EDP, the product of energy consumption and circuit delay) for decades. However, continued silicon scaling is becoming increasingly challenging. This is motivating the search for beyond-silicon nanotechnologies, such as one-dimensional carbon nanotubes (CNTs) or two-dimensional nanomaterials such as transition metal dichalcogenides (TMDs). Yet simply relying on new materials alone is insufficient for realizing the next generation of energy-efficient computing. Rather, coordinated advances across the entire computing system stack are required, as their combined benefits are greater than the sum of their individual benefits.

Name thesis:degree_name

Master

Department dc:contributor.department

Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2019

Author dc:creator

• Kanhaiya, Pritpal(Pritpal Singh).

Advisor dc:contributor.advisor

• Max M. Shulaker.

• Electrical Engineering and Computer Science.

Statement dc:rights

• MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

https://hdl.handle.net/1721.1/122552

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/122552