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Massachusetts Institute of Technology

Flexible options in semiconductor design

Abstract

dc:description.abstract

In semiconductor design, system architects must find the right balance between competing goals [1]: 1. Creating customer value with low average development costs to minimize overhead over a range of products. 2. Fulfilling customer demand with the lowest per unit cost to maximize profit. 3. Exceeding customer expectations to increase market opportunity and drive future growth. As the cost for semiconductor development and investment increases, so does the uncertainty of market success for new products. In this risky environment, a flexible design that increases market opportunity is potentially highly valuable. Flexible designs allow system architects to defer decisions about the exact system configuration and functionality which in turn minimizes the downside effects associated with unforeseen changes in market demand and promotes learning opportunities which lower per unit cost over time [2].

Degree

thesis:*
Name thesis:degree_name
Master
Department dc:contributor.department
Massachusetts Institute of Technology. Engineering and Management Program
Grantor dc:publisher
Massachusetts Institute of Technology
Year dc:date.issued
2019

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • McShea, Matthew D.
Advisor dc:contributor.advisor
  • Richard de Neufville.

Subjects

dc:subject × 2

Rights

dc:rights
Statement dc:rights
  • MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission.
Language dc:language.iso
eng

Identifiers

dc:identifier.*
Handle dc:identifier.uri
https://hdl.handle.net/1721.1/122247
OAI identifier oai:identifier
oai:dspace.mit.edu:1721.1/122247

Chain of custody

source
Harvested from
MIT
Base URL
dspace.mit.edu/oai/request
Last updated
2026-07-22
Source record
OAI-PMH GetRecord
citation

McShea, Matthew D.. Flexible options in semiconductor design. Massachusetts Institute of Technology, 2019. https://hdl.handle.net/1721.1/122247