A high frequency variable load inverter architecture

This thesis presents a high frequency variable load inverter architecture along with a physical prototype and eciency optimizing controller. The inverter architecture consists of two constituent inverters, one connected directly through the load and the other connected through an immittance converter, which acts as a lossless power combiner. By controlling the amplitude and relative phase of the two constituent inverters the loading seen by each constituent inverter can be kept in a desirable range for wide variations in load impedance. This allows for the use of highly ecient zero voltage switching inverters that would otherwise be precluded in applications with widely varying load impedances, such as wireless power transfer and plasma generation. Previous solutions to the challenge of driving widely variable load impedances, such as the tunable matching network, have typically resulted in systems that are often bulky, expensive, and slow. The physical prototype developed for this project operates at 13.56MHz and can supply a maximum output power of 1kW into a 21:8 + 0:3j load at an eciency of 95:4%. The eciency optimizing controller utilizes a quasi-static model prediction approach which allows for optimization of system performance over any desirable parameter. The system is also capable of driving a wide range of capacitive and inductive loads at a high power level and with high efficiency.

Name thesis:degree_name

Master

Department dc:contributor.department

Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2018

Author dc:creator

• Braun, Weston D.

Advisor dc:contributor.advisor

• David J. Perreault.

• Electrical Engineering and Computer Science.

Statement dc:rights

• MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

https://hdl.handle.net/1721.1/121623

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/121623