Development of a scalable superconducting memory

Superconducting computers promise very high computation speeds while also consuming far less power than their conventional counterparts. However, much of the progress in this field has been stymied by the lack of a scalable superconducting memory technology. In this thesis, I present the design of, and demonstrate the operation of, a superconducting nanowire-based memory cell. In contrast to existing designs, this cell operates by means of kinetic rather than geometric inductance. Thus, the cell size can be made much smaller than would otherwise be possible. With the successful operation of the single cell, paths to larger arrays are explored, and a small array demonstrated. The further development of the technology demonstrated in this work will allow for the production of large-scale superconducting processors, and the eventual development of superconducting supercomputers.

Department dc:contributor.department

Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2018

Author dc:creator

• Butters, Brenden A

Advisor dc:contributor.advisor

• Karl K. Berggren.

• Electrical Engineering and Computer Science.

Statement dc:rights

• MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/120406

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/120406