Creation, validation, and implementation of a Highly Accelerated Life Testing (HALT) procedure to improve the reliability of printed circuit boards

Highly Accelerated Life Testing (HALT) is a test methodology to evaluate the reliability of electronic and electromechanical devices. This thesis aimed at the implementation of Highly Accelerated Life Testing (HALT) on Printed Circuit Boards. A standard operating procedure for implementing Highly Accelerated Life Testing (HALT) to increase the reliability of PCBs used in various Waters equipment is developed and validated. For the creation of the standard operating procedure a very reliable Alliance PCB is selected that acts as a benchmark for screening other boards. Extensive testing is done on the Alliance PCB by subjecting it to thermal and vibration stresses through a Hot Step Stress profile, Cold Step Stress profile, Thermal Cycling, Vibration Step Stress profile and Combined Cycle profile. For validation, the standard operating procedure created is applied to a less reliable Acquity board to check whether the same standard operating procedure is effective in precipitating and detecting failures on a variety of different boards that Waters equipment uses. As expected the operating limits of temperature and vibration of the Acquity board are found to be less than the Alliance board i.e. the Acquity experiences failure much earlier than Alliance when subjected to the same stress profiles. This result is in direct correlation with the on field failure data obtained for these two boards - the less reliable board has lesser operating limits.

Department dc:contributor.department

Massachusetts Institute of Technology. Department of Mechanical Engineering.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2016

Author dc:creator

• Singh, Abhishek, M. Eng. Massachusetts Institute of Technology

Advisor dc:contributor.advisor

• David E. Hardt.

• Mechanical Engineering.

Statement dc:rights

• MIT theses are protected by copyright. They may be viewed, downloaded, or printed from this source but further reproduction or distribution in any format is prohibited without written permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/107079

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/107079