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Massachusetts Institute of Technology, Laboratory for Information and Decision Systems
Full utilization, fairness, and access delay on high speed slotted bus networks
Abstract
dc:descriptionThesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.
Degree
thesis:*- Department dc:contributor.department
- Massachusetts Institute of Technology. Laboratory for Information and Decision Systems
- Grantor dc:publisher
- Massachusetts Institute of Technology, Laboratory for Information and Decision Systems
- Year dc:date.issued
- 1997
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Chiu, Angela Lan
Subjects
dc:subject × 1Rights
dc:rights- Statement dc:rights
-
- M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
- Licence dc:rights.uri
- Language dc:language.iso
- eng
Identifiers
dc:identifier.*- Dc Identifier Other
- 2382
- OAI identifier oai:identifier
- oai:dspace.mit.edu:1721.1/10699