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Massachusetts Institute of Technology

Synchronization in timestamp-based cache coherence protocols

Abstract

dc:description.abstract

Supporting computationally demanding workloads into the future requires that multiprocessor systems support hundreds or thousands of cores. A cache coherence protocol manages the memory cached by these many cores, but the storage overhead required by existing directory-based protocols to track coherence state scales poorly as the number of cores increases. The Tardis cache coherence protocol uses timestamps to avoid these scalability problems. We build a cycle-level multicore simulator that implements a version of the Tardis protocol that uses release consistency. Changing the coherence protocol, which affects what memory values a processor can observe, changes inter-processor communication and synchronization, two processes crucial to the operation of a multicore system. We construct Tardis versions of synchronization primitives and the atomic instructions they use, and compare them to their analogous implementations on a directory-based cache coherent multicore system. Simulations on several benchmarks suggest that the Tardis system performs just as well as the baseline system while preserving the ability to scale systems to hundreds or thousands of cores.

Degree

thesis:*
Department dc:contributor.department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Grantor dc:publisher
Massachusetts Institute of Technology
Year dc:date.issued
2016

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Nguyen, Quan Minh (Scientist in electrical engineering and computer science) Massachusetts Institute of Technology
Advisor dc:contributor.advisor
  • Srinivas Devadas.

Subjects

dc:subject × 1

Rights

dc:rights
Statement dc:rights
  • M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
Language dc:language.iso
eng

Identifiers

dc:identifier.*
Handle dc:identifier.uri
http://hdl.handle.net/1721.1/106086
OAI identifier oai:identifier
oai:dspace.mit.edu:1721.1/106086

Chain of custody

source
Harvested from
MIT
Base URL
dspace.mit.edu/oai/request
Last updated
2026-07-22
Source record
OAI-PMH GetRecord
citation

Nguyen, Quan Minh (Scientist in electrical engineering and computer science) Massachusetts Institute of Technology. Synchronization in timestamp-based cache coherence protocols. Massachusetts Institute of Technology, 2016. http://hdl.handle.net/1721.1/106086