{"id":{"repo_id":"mit","oai_identifier":"oai:dspace.mit.edu:1721.1/101588"},"canonical_url":"https://search.dev.ndltd.org/etd/mit/oai:dspace.mit.edu:1721.1/101588","repository":{"repo_id":"mit","name":"MIT","base_url":"https://dspace.mit.edu/oai/request"},"display":{"title":"Physical redundancy for defect tolerance : example designs and fundamental limits","abstract":"This project analyzes designs for physical redundancy which are modeled abstractly as a bipartite graph. The goal is to determine the characteristics of graph structures which optimize the trade-off between the number of edges and the number of redundant components or nodes needed while correcting a deterministic number of worst-case errors. This thesis looks at finite-sized designs, asymptotically large designs with finite error correcting values, and designs with asymptotically large error correcting values. Results include some small optimal graph structures and fundamental limits on what the optimal design structure can achieve for the cases where a small number of errors are corrected and for where the number of errors to be correctly grows asymptotically.","abstract_html":"This project analyzes designs for physical redundancy which are modeled abstractly as a bipartite graph. The goal is to determine the characteristics of graph structures which optimize the trade-off between the number of edges and the number of redundant components or nodes needed while correcting a deterministic number of worst-case errors. This thesis looks at finite-sized designs, asymptotically large designs with finite error correcting values, and designs with asymptotically large error correcting values. Results include some small optimal graph structures and fundamental limits on what the optimal design structure can achieve for the cases where a small number of errors are corrected and for where the number of errors to be correctly grows asymptotically.","abstract_has_math":false,"creators":["Tang, Jennifer (Jennifer Susan)"],"institution":"Massachusetts Institute of Technology","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.","school":null,"contributors":[],"advisors":["Yury Polyanskiy."],"committee_chairs":[],"committee_members":[],"year":2015,"date_issued":"2015","date_published":"2015","updated_at":"2026-07-22T22:21:44Z","subjects":["Electrical Engineering and Computer Science."],"languages":["eng"],"rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"rights_urls":["http://dspace.mit.edu/handle/1721.1/7582"],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/1721.1/101588","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Yury Polyanskiy."]},{"key":"dc:contributor.department","label":"Department","values":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science."]},{"key":"dc:contributor.other","label":"Dc Contributor Other","values":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science."]},{"key":"dc:creator","label":"Author","values":["Tang, Jennifer (Jennifer Susan)"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2016-03-03T21:10:43Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2016-03-03T21:10:43Z"]},{"key":"dc:date.issued","label":"Date","values":["2015"]},{"key":"dc:publisher","label":"Institution","values":["Massachusetts Institute of Technology"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Electrical Engineering and Computer Science."]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://dspace.mit.edu/handle/1721.1/7582"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/1721.1/101588"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.","Cataloged from PDF version of thesis.","Includes bibliographical references (page 75)."]},{"key":"dc:description.abstract","label":"Abstract","values":["This project analyzes designs for physical redundancy which are modeled abstractly as a bipartite graph. The goal is to determine the characteristics of graph structures which optimize the trade-off between the number of edges and the number of redundant components or nodes needed while correcting a deterministic number of worst-case errors. This thesis looks at finite-sized designs, asymptotically large designs with finite error correcting values, and designs with asymptotically large error correcting values. Results include some small optimal graph structures and fundamental limits on what the optimal design structure can achieve for the cases where a small number of errors are corrected and for where the number of errors to be correctly grows asymptotically."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["S.M."]},{"key":"dc:title","label":"Title","values":["Physical redundancy for defect tolerance : example designs and fundamental limits"]}]}],"canonical_facts":{"dc:contributor.advisor":["Yury Polyanskiy."],"dc:contributor.department":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science."],"dc:contributor.other":["Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science."],"dc:creator":["Tang, Jennifer (Jennifer Susan)"],"dc:date.accessioned":["2016-03-03T21:10:43Z"],"dc:date.available":["2016-03-03T21:10:43Z"],"dc:date.issued":["2015"],"dc:description":["Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.","Cataloged from PDF version of thesis.","Includes bibliographical references (page 75)."],"dc:description.abstract":["This project analyzes designs for physical redundancy which are modeled abstractly as a bipartite graph. The goal is to determine the characteristics of graph structures which optimize the trade-off between the number of edges and the number of redundant components or nodes needed while correcting a deterministic number of worst-case errors. This thesis looks at finite-sized designs, asymptotically large designs with finite error correcting values, and designs with asymptotically large error correcting values. Results include some small optimal graph structures and fundamental limits on what the optimal design structure can achieve for the cases where a small number of errors are corrected and for where the number of errors to be correctly grows asymptotically."],"dc:description.degree":["S.M."],"dc:identifier.uri":["http://hdl.handle.net/1721.1/101588"],"dc:language.iso":["eng"],"dc:publisher":["Massachusetts Institute of Technology"],"dc:rights":["M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission."],"dc:rights.uri":["http://dspace.mit.edu/handle/1721.1/7582"],"dc:subject":["Electrical Engineering and Computer Science."],"dc:title":["Physical redundancy for defect tolerance : example designs and fundamental limits"],"dc:type":["Thesis"]},"updated_at":"2026-07-22T22:21:44Z"}