{"id":{"repo_id":"maryland","oai_identifier":"oai:drum.lib.umd.edu:1903/7185"},"canonical_url":"https://search.dev.ndltd.org/etd/maryland/oai:drum.lib.umd.edu:1903/7185","repository":{"repo_id":"maryland","name":"University of Maryland","base_url":"https://api.drum.lib.umd.edu/server/oai/request"},"display":{"title":"Integrating a Dual-Vth Design Flow Using Mixed Vth Cell Libraries in EDA Tool","abstract":"Leakage power has become one of the most important components of power dissipation in sub-micron designs. It is critical to include leakage mitigation methods in the low power design flow. Dual-Vth assignment, an effective leakage reduction technique, has been adopted by industrial EDA tools in gate-level design. This thesis presents a dual-Vth based low leakage design flow using a mixed Vth standard cell library, in which transistors within a cell have different Vth values. A mixed threshold standard cell design methodology is implemented and the cells are characterized using HSPICE with 130nm model. We integrated the design flow in a state-of-the-art industrial CAD tool and ran experiments on eleven ISCAS benchmarks and three industrial designs. On an average, our method can achieve 40% leakage saving over designs with nominal threshold voltage cells and 9% saving over the cell-based dual-Vth assignment technique, without any delay penalty.","abstract_html":"Leakage power has become one of the most important components of power dissipation in sub-micron designs. It is critical to include leakage mitigation methods in the low power design flow. Dual-Vth assignment, an effective leakage reduction technique, has been adopted by industrial EDA tools in gate-level design. This thesis presents a dual-Vth based low leakage design flow using a mixed Vth standard cell library, in which transistors within a cell have different Vth values. A mixed threshold standard cell design methodology is implemented and the cells are characterized using HSPICE with 130nm model. We integrated the design flow in a state-of-the-art industrial CAD tool and ran experiments on eleven ISCAS benchmarks and three industrial designs. On an average, our method can achieve 40% leakage saving over designs with nominal threshold voltage cells and 9% saving over the cell-based dual-Vth assignment technique, without any delay penalty.","abstract_has_math":false,"creators":["Nagarajan, Chandra S"],"institution":null,"degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Electrical Engineering","school":null,"contributors":[],"advisors":["Qu, Gang"],"committee_chairs":[],"committee_members":[],"year":2007,"date_issued":"2007-06-04","date_published":"2007-06-04","updated_at":"2026-07-24T03:02:08Z","subjects":[],"languages":["en_US"],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/1903/7185","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Qu, Gang"]},{"key":"dc:contributor.department","label":"Department","values":["Electrical Engineering"]},{"key":"dc:creator","label":"Author","values":["Nagarajan, Chandra S"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2007-09-28T14:57:08Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2007-09-28T14:57:08Z"]},{"key":"dc:date.issued","label":"Date","values":["2007-06-04"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en_US"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/1903/7185"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["Leakage power has become one of the most important components of power dissipation in sub-micron designs. It is critical to include leakage mitigation methods in the low power design flow. Dual-Vth assignment, an effective leakage reduction technique, has been adopted by industrial EDA tools in gate-level design. This thesis presents a dual-Vth based low leakage design flow using a mixed Vth standard cell library, in which transistors within a cell have different Vth values. A mixed threshold standard cell design methodology is implemented and the cells are characterized using HSPICE with 130nm model. We integrated the design flow in a state-of-the-art industrial CAD tool and ran experiments on eleven ISCAS benchmarks and three industrial designs. On an average, our method can achieve 40% leakage saving over designs with nominal threshold voltage cells and 9% saving over the cell-based dual-Vth assignment technique, without any delay penalty."]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Integrating a Dual-Vth Design Flow Using Mixed Vth Cell Libraries in EDA Tool"]}]}],"canonical_facts":{"dc:contributor.advisor":["Qu, Gang"],"dc:contributor.department":["Electrical Engineering"],"dc:creator":["Nagarajan, Chandra S"],"dc:date.accessioned":["2007-09-28T14:57:08Z"],"dc:date.available":["2007-09-28T14:57:08Z"],"dc:date.issued":["2007-06-04"],"dc:description.abstract":["Leakage power has become one of the most important components of power dissipation in sub-micron designs. It is critical to include leakage mitigation methods in the low power design flow. Dual-Vth assignment, an effective leakage reduction technique, has been adopted by industrial EDA tools in gate-level design. This thesis presents a dual-Vth based low leakage design flow using a mixed Vth standard cell library, in which transistors within a cell have different Vth values. A mixed threshold standard cell design methodology is implemented and the cells are characterized using HSPICE with 130nm model. We integrated the design flow in a state-of-the-art industrial CAD tool and ran experiments on eleven ISCAS benchmarks and three industrial designs. On an average, our method can achieve 40% leakage saving over designs with nominal threshold voltage cells and 9% saving over the cell-based dual-Vth assignment technique, without any delay penalty."],"dc:format.mimetype":["application/pdf"],"dc:identifier.uri":["http://hdl.handle.net/1903/7185"],"dc:language.iso":["en_US"],"dc:title":["Integrating a Dual-Vth Design Flow Using Mixed Vth Cell Libraries in EDA Tool"],"dc:type":["Thesis"]},"updated_at":"2026-07-24T03:02:08Z"}