Continuous-Time Delta-Sigma Modulators for Ultra-Low-Power Radios
The modern small devices of today require cheap low power radio frequency (RF) transceivers that can provide reliable connectivity at all times. In an RF transceiver, the analog-to-digital converter (ADC) is one of the most important parts and it is also one of the main power consumers. There are several architectures for implementing an ADC, but in the last decade, continuous-time Delta-Sigma modulators (CT DSMs) have become popular due to their potential of achieving low power consumption and the inherent anti-alias filtering. This thesis investigates different implementations of CT DSMs intended for an ultra-low-power (ULP) receiver operating in the 2.45 GHz ISM band. The main focus is on power saving techniques and jitter insensitive solutions. Papers I and II present a CT DSM with dual switched-capacitor-resistor (DSCR) feedback used in the first DAC. This technique has been developed for the purpose of reducing the jitter sensitivity of the CT DSM while keeping the DAC peak current lower than for conventional SCR feedback. A lower peak current translates into more relaxed slew-rate requirements on the first operational amplifier and thereby less power consumption. Papers III and IV present a low power 2nd-order CT DSM with one operational amplifier. The main objective was to reduce the power consumption of the usually more critical analog part while still achieving a 2nd-order noise shaping. The thesis also examines the possibility of using a successive approximation register (SAR) quantizer instead of the commonly used flash quantizer to reduce the power consumption of the digital part as well.
Electrical Engineering, Electronic Engineering, Information Engineering, Delta-Sigma, continuous-time, analog-to-digital, ultra-low-power, clock jitter, single operational amplifier, SAR quantizer
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Department of Electrical and Information Technology, Lund University