CMOS Transceiver Front-Ends in Mobile Communication Handsets - Architectures and Building Blocks

For mobile communication systems in the low-GHz range, CMOS has increasingly become the technology of choice, and the level of integration in mobile handsets has risen. The use of off-chip components, which increases the handset assembly time and costs, is preferably avoided. However, integrating a complete transceiver on a single chip leads to disturbances between building blocks. This imposes new and more stringent requirements on building block and transceiver performance, as well as impacts the choice of transceiver architecture. In the general introduction, an overview is given of front-end receiver and transmitter aspects as well as RF CMOS technology. This includes the impact of mobile communication system specifications on architectures and building blocks, transistor and monolithic inductor modeling, and disturbance issues. Special attention is given to power amplifiers, the most challenging building blocks in CMOS transceivers. Papers I, II and III address CMOS receiver front-end aspects and implementations, while in papers IV and V design and challenges of CMOS power amplifiers are described.

Grantor dc:publisher

Department of Electroscience, Lund University

Year dc:date

2004

Author dc:creator

• Cijvat, Pieternella

• Electrical Engineering, Electronic Engineering, Information Engineering
• RF CMOS
• Wireless Communication
• Receiver
• Transmitter
• Power Amplifier
• Harmonic Distortion
• Electrical engineering
• Elektroteknik
• Telecommunication engineering
• Telekommunikationsteknik

Statement dc:rights

• info:eu-repo/semantics/openAccess

Language dc:language

eng

Repository record dc:identifier

https://lup.lub.lu.se/record/467657

OAI identifier oai:identifier

oai:lup.lub.lu.se:a8bd79be-13a2-420e-b62f-fba1d240bc3d