Development of electrical characterization techniques for lifetime prediction and understanding defects in InGaAs-based III-V transistors

Combining the advanced complementary metal-oxide-semiconductor (CMOS) technique, faster and highly packaged circuits have continuous developing for more than fifty years. During this period time, engineers focus on the higher electrical field and accelerate the degradation to make the highly performance of advanced CMOS devices with better and smaller size than before. At this moment, there are plenty of issues are found which can affect the performances ofthe device. For example, for the new material technique, people prefe tor use III-V materials to instead of the traditional silicon, and for the traditional CMOS device, the main reliability issue is bias temperature instability (BTI), NBTI for pMOS and PBTI for nMOS. Therefore, this thesis will talk about investigating the NBTI/PBTI and III-V device performance and lifetime prediction issues. For the whole ofthe thesis, it can be divided by 4 chapters to describe the details, the first chapter would be the introduction of background knowledge and current understanding for how the traditional CMOS device works, and why the new materials could be instead, like III-V device, it shows the advantages and disadvantages for each of them. Moreover, there are some other information would be explained, such as Discharging-based multiple pulse (DMP) method, and hot carrier stress. Those are also topics and directions relate tod this thesis for the further research. Chapter 2 shows a new measurement method, which called Fast reliability screening technique method (VSS). It compared the conventional measurement method, which is constant voltage stress (CVS), is faster and only use a single device. And it also combined the measurement details and results to show that method is more efficiently, which includes the benefits and parameters discussion in the different conditions. Chapter 3 shows a separation traps method of III-V devices with in In0.53Ga0.47As channel. In this chapter, firstly, it shows the introduction of III-V devices for the basic theory and working function, then there are some experiments, which include both AC and DC measurements to show the III-V devices have very fast recovery abilities. Then because of the recovery ability, the devices would work well after charging and discharging even after heavily stress and long stress time. Moreover, combine the different discharge voltage levels to get the whole border trap energy distribution. After that, the chapter 3 shows how to separate the traps into two different types, type A and type B. there are experiments results and details to show how it is divided. Then it also mentioned the method can work with different stress time, channel thickness and temperature dependence. In Chapter 4, the discussion and a summary about previous work has been given, which also points out the future research plans and directions. It includes the lifetime prediction under slow and fast measurements for III-V devices.

Name dc:type.qualificationname

mphil

Level dc:type.qualificationlevel

doctoral

Grantor dc:publisher.institution

Liverpool John Moores University

Year dc:date.issued

2019

Author dc:creator

• Zhang, X

Contributors dc:contributor

• Ji, Z

• TK Electrical engineering. Electronics. Nuclear engineering

DOI dc:identifier.doi

https://doi.org/10.24377/LJMU.t.00010186

OAI identifier oai:identifier

oai:researchonline.ljmu.ac.uk:10186