{"id":{"repo_id":"lethbridge","oai_identifier":"oai:opus.uleth.ca:10133/7148"},"canonical_url":"https://search.dev.ndltd.org/etd/lethbridge/oai:opus.uleth.ca:10133/7148","repository":{"repo_id":"lethbridge","name":"University of Lethbridge","base_url":"https://opus.uleth.ca/server/oai/request"},"display":{"title":"Reconfigurable and compact modular polynomial multiplier in Galois field for the security of IoT","abstract":"The rise of the Internet of Things (IoT) has intensified the need for secure, low-power cryptographic hardware capable of operating efficiently in constrained environments. This thesis presents the design and implementation of reconfigurable and compact modular polynomial multipliers over Galois Fields (GF), specifically tailored for the security demands of IoT devices. Leveraging polynomial basis arithmetic in GF(2m), the proposed designs emphasize hardware efficiency, adaptability, and cryptographic robustness for Elliptic Curve Cryptography (ECC) applications. The proposed multipliers were synthesized and validated on multiple FPGA platforms including Spartan-7, Zynq UltraScale+, and Artix-7 using the AMD Xilinx Vivado toolchain. The Karatsuba reconfigurable multiplier achieved the best area-delay product (ADP) across platforms. Analytical and experimental comparisons confirm that the reconfigurable approaches significantly outperform conventional designs in terms of efficiency and scalability. This research provides a practical and versatile foundation for cryptographic accelerators in future low-power and high-security IoT systems.","abstract_html":"The rise of the Internet of Things (IoT) has intensified the need for secure, low-power cryptographic hardware capable of operating efficiently in constrained environments. This thesis presents the design and implementation of reconfigurable and compact modular polynomial multipliers over Galois Fields (GF), specifically tailored for the security demands of IoT devices. Leveraging polynomial basis arithmetic in GF(2m), the proposed designs emphasize hardware efficiency, adaptability, and cryptographic robustness for Elliptic Curve Cryptography (ECC) applications. The proposed multipliers were synthesized and validated on multiple FPGA platforms including Spartan-7, Zynq UltraScale+, and Artix-7 using the AMD Xilinx Vivado toolchain. The Karatsuba reconfigurable multiplier achieved the best area-delay product (ADP) across platforms. Analytical and experimental comparisons confirm that the reconfigurable approaches significantly outperform conventional designs in terms of efficiency and scalability. This research provides a practical and versatile foundation for cryptographic accelerators in future low-power and high-security IoT systems.","abstract_has_math":false,"creators":["Haroon, Fariha","University of Lethbridge. Faculty of Arts and Science"],"institution":null,"degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":null,"school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2025,"date_issued":"2025","date_published":"2025","updated_at":"2026-07-27T20:02:45Z","subjects":["polynomial modular multiplier","elliptic curve cryptography","Galois fields","Internet of Things","FPGA"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["hdl:10133/7148"],"render_values":[{"text":"hdl:10133/7148","href":null,"code":true}]}]},"links":{"outbound_url":null,"outbound_label":null,"outbound_source":null},"metadata_groups":[{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.issued","label":"Date","values":["2025"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["polynomial modular multiplier","elliptic curve cryptography","Galois fields","Internet of Things","FPGA"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["hdl:10133/7148"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.other","label":"Dc Description Other","values":["The rise of the Internet of Things (IoT) has intensified the need for secure, low-power cryptographic hardware capable of operating efficiently in constrained environments. This thesis presents the design and implementation of reconfigurable and compact modular polynomial multipliers over Galois Fields (GF), specifically tailored for the security demands of IoT devices. Leveraging polynomial basis arithmetic in GF(2m), the proposed designs emphasize hardware efficiency, adaptability, and cryptographic robustness for Elliptic Curve Cryptography (ECC) applications. The proposed multipliers were synthesized and validated on multiple FPGA platforms including Spartan-7, Zynq UltraScale+, and Artix-7 using the AMD Xilinx Vivado toolchain. The Karatsuba reconfigurable multiplier achieved the best area-delay product (ADP) across platforms. Analytical and experimental comparisons confirm that the reconfigurable approaches significantly outperform conventional designs in terms of efficiency and scalability. This research provides a practical and versatile foundation for cryptographic accelerators in future low-power and high-security IoT systems."]},{"key":"dc:title","label":"Title","values":["Reconfigurable and compact modular polynomial multiplier in Galois field for the security of IoT"]}]}],"canonical_facts":{"dc:date.issued":["2025"],"dc:description.other":["The rise of the Internet of Things (IoT) has intensified the need for secure, low-power cryptographic hardware capable of operating efficiently in constrained environments. This thesis presents the design and implementation of reconfigurable and compact modular polynomial multipliers over Galois Fields (GF), specifically tailored for the security demands of IoT devices. Leveraging polynomial basis arithmetic in GF(2m), the proposed designs emphasize hardware efficiency, adaptability, and cryptographic robustness for Elliptic Curve Cryptography (ECC) applications. The proposed multipliers were synthesized and validated on multiple FPGA platforms including Spartan-7, Zynq UltraScale+, and Artix-7 using the AMD Xilinx Vivado toolchain. The Karatsuba reconfigurable multiplier achieved the best area-delay product (ADP) across platforms. Analytical and experimental comparisons confirm that the reconfigurable approaches significantly outperform conventional designs in terms of efficiency and scalability. This research provides a practical and versatile foundation for cryptographic accelerators in future low-power and high-security IoT systems."],"dc:identifier":["hdl:10133/7148"],"dc:subject":["polynomial modular multiplier","elliptic curve cryptography","Galois fields","Internet of Things","FPGA"],"dc:title":["Reconfigurable and compact modular polynomial multiplier in Galois field for the security of IoT"],"dc:type":["Thesis"]},"updated_at":"2026-07-27T20:02:45Z"}