{"id":{"repo_id":"lethbridge","oai_identifier":"oai:opus.uleth.ca:10133/5022"},"canonical_url":"https://search.dev.ndltd.org/etd/lethbridge/oai:opus.uleth.ca:10133/5022","repository":{"repo_id":"lethbridge","name":"University of Lethbridge","base_url":"https://opus.uleth.ca/server/oai/request"},"display":{"title":"Synthesis, testing and tolerance in reversible logic","abstract":"In recent years, reversible computing has established itself as a promising research area and emerging technology. This thesis focuses on three important areas of reversible logic, which is an area of reversible computing. Firstly, this thesis proposes a transformation based synthesis approach for realizing conservative reversible functions using SWAP and Fredkin gates. This thesis also proposes ten templates for optimizing SWAP and Fredkin gates-based reversible circuits. Secondly, this thesis proposes an approach for the design of online testable reversible circuits. A reversible circuit composed of NOT, CNOT and Toffoli gates can be made online testable by adding two sets of CNOT gates and a single parity line. Finally, we have proposed an approach to achieve fault tolerance in reversible circuits. A design of a 3-bit reversible majority voter circuit is presented. This voter circuit can be used to design fault tolerant reversible circuits.","abstract_html":"In recent years, reversible computing has established itself as a promising research area and emerging technology. This thesis focuses on three important areas of reversible logic, which is an area of reversible computing. Firstly, this thesis proposes a transformation based synthesis approach for realizing conservative reversible functions using SWAP and Fredkin gates. This thesis also proposes ten templates for optimizing SWAP and Fredkin gates-based reversible circuits. Secondly, this thesis proposes an approach for the design of online testable reversible circuits. A reversible circuit composed of NOT, CNOT and Toffoli gates can be made online testable by adding two sets of CNOT gates and a single parity line. Finally, we have proposed an approach to achieve fault tolerance in reversible circuits. A design of a 3-bit reversible majority voter circuit is presented. This voter circuit can be used to design fault tolerant reversible circuits.","abstract_has_math":false,"creators":["Nashiry, Md Asif","University of Lethbridge. Faculty of Arts and Science"],"institution":null,"degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":null,"school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2017,"date_issued":"2017","date_published":"2017","updated_at":"2026-07-27T20:02:23Z","subjects":["Reversible computing","Dissertations, Academic"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["hdl:10133/5022"],"render_values":[{"text":"hdl:10133/5022","href":null,"code":true}]}]},"links":{"outbound_url":null,"outbound_label":null,"outbound_source":null},"metadata_groups":[{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.issued","label":"Date","values":["2017"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Reversible computing","Dissertations, Academic"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["hdl:10133/5022"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.other","label":"Dc Description Other","values":["In recent years, reversible computing has established itself as a promising research area and emerging technology. This thesis focuses on three important areas of reversible logic, which is an area of reversible computing. Firstly, this thesis proposes a transformation based synthesis approach for realizing conservative reversible functions using SWAP and Fredkin gates. This thesis also proposes ten templates for optimizing SWAP and Fredkin gates-based reversible circuits. Secondly, this thesis proposes an approach for the design of online testable reversible circuits. A reversible circuit composed of NOT, CNOT and Toffoli gates can be made online testable by adding two sets of CNOT gates and a single parity line. Finally, we have proposed an approach to achieve fault tolerance in reversible circuits. A design of a 3-bit reversible majority voter circuit is presented. This voter circuit can be used to design fault tolerant reversible circuits."]},{"key":"dc:title","label":"Title","values":["Synthesis, testing and tolerance in reversible logic"]}]}],"canonical_facts":{"dc:date.issued":["2017"],"dc:description.other":["In recent years, reversible computing has established itself as a promising research area and emerging technology. This thesis focuses on three important areas of reversible logic, which is an area of reversible computing. Firstly, this thesis proposes a transformation based synthesis approach for realizing conservative reversible functions using SWAP and Fredkin gates. This thesis also proposes ten templates for optimizing SWAP and Fredkin gates-based reversible circuits. Secondly, this thesis proposes an approach for the design of online testable reversible circuits. A reversible circuit composed of NOT, CNOT and Toffoli gates can be made online testable by adding two sets of CNOT gates and a single parity line. Finally, we have proposed an approach to achieve fault tolerance in reversible circuits. A design of a 3-bit reversible majority voter circuit is presented. This voter circuit can be used to design fault tolerant reversible circuits."],"dc:identifier":["hdl:10133/5022"],"dc:subject":["Reversible computing","Dissertations, Academic"],"dc:title":["Synthesis, testing and tolerance in reversible logic"],"dc:type":["Thesis"]},"updated_at":"2026-07-27T20:02:23Z"}