{"id":{"repo_id":"houston","oai_identifier":"oai:uh-ir.tdl.org:10657/19523"},"canonical_url":"https://search.dev.ndltd.org/etd/houston/oai:uh-ir.tdl.org:10657/19523","repository":{"repo_id":"houston","name":"University of Houston","base_url":"https://uh-ir.tdl.org/server/oai/request"},"display":{"title":"FPGA Implementation and Optimization of Bit Flipping Key Generation Algorithm for Post Quantum Cryptography in Embedded Systems Applications","abstract":"The expeditious advancement of quantum computing has created a threat to classic cryptographic systems, calling for post-quantum cryptography (PQC) solutions like Bit Flipping Key Encapsulation (BIKE) algorithm, which utilizes Quasi-Cyclic Moderate Density Parity-Check (QC-MCPC) codes for a secure key exchange. Even though BIKE has cryptographic strengths like structural simplicity, and compact key sizes, it suffers from high dynamic power consumption due to its computationally intensive modular arithmetic operations, which include polynomial multiplication, inversion, and hashing. These factors limits its FPGA implementation power for embedded and IoT applications. This research work presents a resource-constrained FPGA implementation of BIKE on the Artix-7 FPGA, designed for integration into an IoT temperature sensor system on the STM32 microcontroller. This work focuses on basic design algorithms such as shift and XOR for polynomial multiplication, Itoh-Tsujii for polynomial inversion, validated through complete simulation of BIKE’s key operations such as key generation, encapsulation, and decapsulation. Although the current implementation focuses on generating a single set of keys and ciphertext per run, it lays a solid foundation for scalable, power-efficient enhancements in the future. This work underscores that even with restrained resources, BIKE can be made realistic, bridging the gap between PQC and real-world embedded systems deployment.","abstract_html":"The expeditious advancement of quantum computing has created a threat to classic cryptographic systems, calling for post-quantum cryptography (PQC) solutions like Bit Flipping Key Encapsulation (BIKE) algorithm, which utilizes Quasi-Cyclic Moderate Density Parity-Check (QC-MCPC) codes for a secure key exchange. Even though BIKE has cryptographic strengths like structural simplicity, and compact key sizes, it suffers from high dynamic power consumption due to its computationally intensive modular arithmetic operations, which include polynomial multiplication, inversion, and hashing. These factors limits its FPGA implementation power for embedded and IoT applications. This research work presents a resource-constrained FPGA implementation of BIKE on the Artix-7 FPGA, designed for integration into an IoT temperature sensor system on the STM32 microcontroller. This work focuses on basic design algorithms such as shift and XOR for polynomial multiplication, Itoh-Tsujii for polynomial inversion, validated through complete simulation of BIKE’s key operations such as key generation, encapsulation, and decapsulation. Although the current implementation focuses on generating a single set of keys and ciphertext per run, it lays a solid foundation for scalable, power-efficient enhancements in the future. This work underscores that even with restrained resources, BIKE can be made realistic, bridging the gap between PQC and real-world embedded systems deployment.","abstract_has_math":false,"creators":["Ravindran, Muhilan 2002-"],"institution":"University of Houston","degree_name":"Master of Science","degree_level":null,"degree_discipline":"Computer and Systems Engineering","degree_department":null,"school":null,"contributors":[],"advisors":["Chen, Yuhua"],"committee_chairs":[],"committee_members":["Krishnamoorthy, Harish Sarma","Chen, Jinghong"],"year":2025,"date_issued":"2025-05","date_published":"2025-05","updated_at":"2026-07-24T02:32:44Z","subjects":["Computer engineering"],"languages":["English"],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/10657/19523","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Chen, Yuhua"]},{"key":"dc:contributor.committeemember","label":"Committee Member","values":["Krishnamoorthy, Harish Sarma","Chen, Jinghong"]},{"key":"dc:creator","label":"Author","values":["Ravindran, Muhilan 2002-"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2025-06-20T21:19:28Z"]},{"key":"dc:date.issued","label":"Date","values":["2025-05"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer and Systems Engineering"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["University of Houston"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Computer engineering"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["English"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["https://hdl.handle.net/10657/19523"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["The expeditious advancement of quantum computing has created a threat to classic cryptographic systems, calling for post-quantum cryptography (PQC) solutions like Bit Flipping Key Encapsulation (BIKE) algorithm, which utilizes Quasi-Cyclic Moderate Density Parity-Check (QC-MCPC) codes for a secure key exchange. Even though BIKE has cryptographic strengths like structural simplicity, and compact key sizes, it suffers from high dynamic power consumption due to its computationally intensive modular arithmetic operations, which include polynomial multiplication, inversion, and hashing. These factors limits its FPGA implementation power for embedded and IoT applications. This research work presents a resource-constrained FPGA implementation of BIKE on the Artix-7 FPGA, designed for integration into an IoT temperature sensor system on the STM32 microcontroller. This work focuses on basic design algorithms such as shift and XOR for polynomial multiplication, Itoh-Tsujii for polynomial inversion, validated through complete simulation of BIKE’s key operations such as key generation, encapsulation, and decapsulation. Although the current implementation focuses on generating a single set of keys and ciphertext per run, it lays a solid foundation for scalable, power-efficient enhancements in the future. This work underscores that even with restrained resources, BIKE can be made realistic, bridging the gap between PQC and real-world embedded systems deployment."]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["FPGA Implementation and Optimization of Bit Flipping Key Generation Algorithm for Post Quantum Cryptography in Embedded Systems Applications"]}]}],"canonical_facts":{"dc:contributor.advisor":["Chen, Yuhua"],"dc:contributor.committeemember":["Krishnamoorthy, Harish Sarma","Chen, Jinghong"],"dc:creator":["Ravindran, Muhilan 2002-"],"dc:date.accessioned":["2025-06-20T21:19:28Z"],"dc:date.issued":["2025-05"],"dc:description.abstract":["The expeditious advancement of quantum computing has created a threat to classic cryptographic systems, calling for post-quantum cryptography (PQC) solutions like Bit Flipping Key Encapsulation (BIKE) algorithm, which utilizes Quasi-Cyclic Moderate Density Parity-Check (QC-MCPC) codes for a secure key exchange. Even though BIKE has cryptographic strengths like structural simplicity, and compact key sizes, it suffers from high dynamic power consumption due to its computationally intensive modular arithmetic operations, which include polynomial multiplication, inversion, and hashing. These factors limits its FPGA implementation power for embedded and IoT applications. This research work presents a resource-constrained FPGA implementation of BIKE on the Artix-7 FPGA, designed for integration into an IoT temperature sensor system on the STM32 microcontroller. This work focuses on basic design algorithms such as shift and XOR for polynomial multiplication, Itoh-Tsujii for polynomial inversion, validated through complete simulation of BIKE’s key operations such as key generation, encapsulation, and decapsulation. Although the current implementation focuses on generating a single set of keys and ciphertext per run, it lays a solid foundation for scalable, power-efficient enhancements in the future. This work underscores that even with restrained resources, BIKE can be made realistic, bridging the gap between PQC and real-world embedded systems deployment."],"dc:format.mimetype":["application/pdf"],"dc:identifier.uri":["https://hdl.handle.net/10657/19523"],"dc:language.iso":["English"],"dc:subject":["Computer engineering"],"dc:title":["FPGA Implementation and Optimization of Bit Flipping Key Generation Algorithm for Post Quantum Cryptography in Embedded Systems Applications"],"dc:type":["Thesis"],"thesis:degree_discipline":["Computer and Systems Engineering"],"thesis:degree_name":["Master of Science"],"thesis:institution_name":["University of Houston"]},"updated_at":"2026-07-24T02:32:44Z"}