{"id":{"repo_id":"gmu","oai_identifier":"oai:MARS:1920/15207"},"canonical_url":"https://search.dev.ndltd.org/etd/gmu/oai:MARS:1920/15207","repository":{"repo_id":"gmu","name":"George Mason University","base_url":"https://mars.gmu.edu/server/oai/request"},"display":{"title":"Fortifying System Security: Exploring Attacks and Desgning Robust Defenses","abstract":"Cyberattacks are the fastest-growing crime in the U.S., costing the economy billions of dollars annually. These attacks use system vulnerabilities to leak Information or steal identity through unauthorized access (AT&T 2024, Microsoft 2021, and Facebook 2019). Although researchers traditionally considered software as the origin of these threats and left hardware as a trusted party, emerging Hardware Trojans and Micro-architectural Attacks have shown that the hardware can be easily leveraged as a source of leakage to compromise the system security. Hence, this dissertation pursues two directions to mitigate hardware vulnerabilities by generating an evasive hardware Trojan and mitigating the micro-architectural attacks.In the first direction, we investigate threats that exploit hardware Trojans (HTs)- a small malicious modification in hardware causing malfunction, leakage of confidential information, or leading to other disastrous consequences- as a source of leakage. To this aim, we question the trustworthiness of ML-based HT detection via a side-channel analysis, which is a widely used approach to detecting HTs since they don’t require a golden chip (reference chips used to verify the design), are non-intrusive, and highly efficient. Therefore, this dissertation introduces an HT obfuscation (HTO) approach to allow HTs to bypass this detection method. Rather than theoretically misleading the model by simulated adversarial traces, a key aspect of our approach is the design and implementation of adversarial noise as part of the circuitry, alongside the HT. We detail HTO methodologies for ASICs and FPGAs and evaluate our approach using the TrustHub benchmark. Interestingly, we found that HTO can be implemented with only a single transistor for ASIC designs to generate adversarial power traces that can fool the defense with 100% efficiency. We also efficiently implemented our approach on a Spartan 6 Xilinx FPGA using 2 different variants: (i) DSP slices-based, and (ii) ring-oscillator-based design. Additionally, we assess the efficiency of countermeasures like spectral domain analysis and adversarial training (AT) on the proposed method. Despite restricting the spectral noise budget can impact the attack efficiency, we show that an adaptive attacker can still design evasive HTOs by constraining the design with a spectral noise budget. In addition, while adversarial training (AT) offers higher protection against evasive HTs, AT models suffer from a considerable utility loss, potentially rendering them unsuitable for such security applications. In the second direction, first, we explore transient execution attacks, such as Spectre and Meltdown, targeting speculative execution (a micro-architectural optimization in modern processors) to access privileged data and leak it through a side channel. To this aim, we present a framework that automates the finding of exploitable Spectre gadgets in a code given a black-box micro-architecture. The main goal is to precisely identify contention-based Spectre gadgets (avoid false positives to reduce the mitigation overhead). We need to focus on finding contention between transiently executed instructions and non-transient ones, which is the type of contention used in transient execution attacks to be able to leak the secret during transient execution. Therefore, the framework enables automation by viewing on-core contention between different instructions, which allows treating the tar- geted CPU micro-architecture as a black box. Specifically, the framework first generates contention maps for a targeted black-box micro-architecture, which show the level of inter- action between each pair of instructions in Instruction Set Architecture (ISA) when one is run transiently and the other runs non-transiently. Subsequently, contention maps are fed into a static code analysis tool that we designed and developed to precisely find exploitable gadgets for a given code when it runs on a given black-box micro-architecture. Second, we propose a generic approach to mitigate micro-architectural side-channel attacks with minimal architectural changes. Unlike traditional approaches that focus on mitigating specific side channels, we propose a dynamic strategy that alters the decoding of the instructions into secure (side-channel resilient) or performance versions of the instructions, based on the data it is processing. Specifically, to minimize performance overhead, decoding to a secure version is selectively applied only when sensitive data is being processed, ensuring optimal performance for instructions operating on non-sensitive data. To evaluate our approach, we implement it on the RISC-V out-of-order BOOM processor. Our results demonstrate that the mechanism increases FPGA resource utilization by only 2% compared to the original design. Additionally, it imposes 0% performance overhead for unprotected applications, while maintaining overhead between up to 25% for security-critical workloads. This work represents a scalable and efficient solution for defending against micro-architectural side-channel attacks without compromising system performance.","abstract_html":"Cyberattacks are the fastest-growing crime in the U.S., costing the economy billions of dollars annually. These attacks use system vulnerabilities to leak Information or steal identity through unauthorized access (AT&T 2024, Microsoft 2021, and Facebook 2019). Although researchers traditionally considered software as the origin of these threats and left hardware as a trusted party, emerging Hardware Trojans and Micro-architectural Attacks have shown that the hardware can be easily leveraged as a source of leakage to compromise the system security. Hence, this dissertation pursues two directions to mitigate hardware vulnerabilities by generating an evasive hardware Trojan and mitigating the micro-architectural attacks.In the first direction, we investigate threats that exploit hardware Trojans (HTs)- a small malicious modification in hardware causing malfunction, leakage of confidential information, or leading to other disastrous consequences- as a source of leakage. To this aim, we question the trustworthiness of ML-based HT detection via a side-channel analysis, which is a widely used approach to detecting HTs since they don’t require a golden chip (reference chips used to verify the design), are non-intrusive, and highly efficient. Therefore, this dissertation introduces an HT obfuscation (HTO) approach to allow HTs to bypass this detection method. Rather than theoretically misleading the model by simulated adversarial traces, a key aspect of our approach is the design and implementation of adversarial noise as part of the circuitry, alongside the HT. We detail HTO methodologies for ASICs and FPGAs and evaluate our approach using the TrustHub benchmark. Interestingly, we found that HTO can be implemented with only a single transistor for ASIC designs to generate adversarial power traces that can fool the defense with 100% efficiency. We also efficiently implemented our approach on a Spartan 6 Xilinx FPGA using 2 different variants: (i) DSP slices-based, and (ii) ring-oscillator-based design. Additionally, we assess the efficiency of countermeasures like spectral domain analysis and adversarial training (AT) on the proposed method. Despite restricting the spectral noise budget can impact the attack efficiency, we show that an adaptive attacker can still design evasive HTOs by constraining the design with a spectral noise budget. In addition, while adversarial training (AT) offers higher protection against evasive HTs, AT models suffer from a considerable utility loss, potentially rendering them unsuitable for such security applications. In the second direction, first, we explore transient execution attacks, such as Spectre and Meltdown, targeting speculative execution (a micro-architectural optimization in modern processors) to access privileged data and leak it through a side channel. To this aim, we present a framework that automates the finding of exploitable Spectre gadgets in a code given a black-box micro-architecture. The main goal is to precisely identify contention-based Spectre gadgets (avoid false positives to reduce the mitigation overhead). We need to focus on finding contention between transiently executed instructions and non-transient ones, which is the type of contention used in transient execution attacks to be able to leak the secret during transient execution. Therefore, the framework enables automation by viewing on-core contention between different instructions, which allows treating the tar- geted CPU micro-architecture as a black box. Specifically, the framework first generates contention maps for a targeted black-box micro-architecture, which show the level of inter- action between each pair of instructions in Instruction Set Architecture (ISA) when one is run transiently and the other runs non-transiently. Subsequently, contention maps are fed into a static code analysis tool that we designed and developed to precisely find exploitable gadgets for a given code when it runs on a given black-box micro-architecture. Second, we propose a generic approach to mitigate micro-architectural side-channel attacks with minimal architectural changes. Unlike traditional approaches that focus on mitigating specific side channels, we propose a dynamic strategy that alters the decoding of the instructions into secure (side-channel resilient) or performance versions of the instructions, based on the data it is processing. Specifically, to minimize performance overhead, decoding to a secure version is selectively applied only when sensitive data is being processed, ensuring optimal performance for instructions operating on non-sensitive data. To evaluate our approach, we implement it on the RISC-V out-of-order BOOM processor. Our results demonstrate that the mechanism increases FPGA resource utilization by only 2% compared to the original design. Additionally, it imposes 0% performance overhead for unprotected applications, while maintaining overhead between up to 25% for security-critical workloads. This work represents a scalable and efficient solution for defending against micro-architectural side-channel attacks without compromising system performance.","abstract_has_math":false,"creators":["Omidi, Behnam"],"institution":null,"degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":null,"school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2025,"date_issued":"2025","date_published":"2025","updated_at":"2026-07-27T19:52:00Z","subjects":["Adversarial Attack","Hardware Trojans","Machine Learning","Micro-architectural Side-channel Attacks","Spectre Attack"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["hdl:1920/15207"],"render_values":[{"text":"hdl:1920/15207","href":null,"code":true}]}]},"links":{"outbound_url":null,"outbound_label":null,"outbound_source":null},"metadata_groups":[{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.issued","label":"Date","values":["2025"]},{"key":"dc:type","label":"Dc Type","values":["Dissertation"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Adversarial Attack","Hardware Trojans","Machine Learning","Micro-architectural Side-channel Attacks","Spectre Attack"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["hdl:1920/15207"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.other","label":"Dc Description Other","values":["Cyberattacks are the fastest-growing crime in the U.S., costing the economy billions of dollars annually. These attacks use system vulnerabilities to leak Information or steal identity through unauthorized access (AT&T 2024, Microsoft 2021, and Facebook 2019). Although researchers traditionally considered software as the origin of these threats and left hardware as a trusted party, emerging Hardware Trojans and Micro-architectural Attacks have shown that the hardware can be easily leveraged as a source of leakage to compromise the system security. Hence, this dissertation pursues two directions to mitigate hardware vulnerabilities by generating an evasive hardware Trojan and mitigating the micro-architectural attacks.In the first direction, we investigate threats that exploit hardware Trojans (HTs)- a small malicious modification in hardware causing malfunction, leakage of confidential information, or leading to other disastrous consequences- as a source of leakage. To this aim, we question the trustworthiness of ML-based HT detection via a side-channel analysis, which is a widely used approach to detecting HTs since they don’t require a golden chip (reference chips used to verify the design), are non-intrusive, and highly efficient. Therefore, this dissertation introduces an HT obfuscation (HTO) approach to allow HTs to bypass this detection method. Rather than theoretically misleading the model by simulated adversarial traces, a key aspect of our approach is the design and implementation of adversarial noise as part of the circuitry, alongside the HT. We detail HTO methodologies for ASICs and FPGAs and evaluate our approach using the TrustHub benchmark. Interestingly, we found that HTO can be implemented with only a single transistor for ASIC designs to generate adversarial power traces that can fool the defense with 100% efficiency. We also efficiently implemented our approach on a Spartan 6 Xilinx FPGA using 2 different variants: (i) DSP slices-based, and (ii) ring-oscillator-based design. Additionally, we assess the efficiency of countermeasures like spectral domain analysis and adversarial training (AT) on the proposed method. Despite restricting the spectral noise budget can impact the attack efficiency, we show that an adaptive attacker can still design evasive HTOs by constraining the design with a spectral noise budget. In addition, while adversarial training (AT) offers higher protection against evasive HTs, AT models suffer from a considerable utility loss, potentially rendering them unsuitable for such security applications. In the second direction, first, we explore transient execution attacks, such as Spectre and Meltdown, targeting speculative execution (a micro-architectural optimization in modern processors) to access privileged data and leak it through a side channel. To this aim, we present a framework that automates the finding of exploitable Spectre gadgets in a code given a black-box micro-architecture. The main goal is to precisely identify contention-based Spectre gadgets (avoid false positives to reduce the mitigation overhead). We need to focus on finding contention between transiently executed instructions and non-transient ones, which is the type of contention used in transient execution attacks to be able to leak the secret during transient execution. Therefore, the framework enables automation by viewing on-core contention between different instructions, which allows treating the tar- geted CPU micro-architecture as a black box. Specifically, the framework first generates contention maps for a targeted black-box micro-architecture, which show the level of inter- action between each pair of instructions in Instruction Set Architecture (ISA) when one is run transiently and the other runs non-transiently. Subsequently, contention maps are fed into a static code analysis tool that we designed and developed to precisely find exploitable gadgets for a given code when it runs on a given black-box micro-architecture. Second, we propose a generic approach to mitigate micro-architectural side-channel attacks with minimal architectural changes. Unlike traditional approaches that focus on mitigating specific side channels, we propose a dynamic strategy that alters the decoding of the instructions into secure (side-channel resilient) or performance versions of the instructions, based on the data it is processing. Specifically, to minimize performance overhead, decoding to a secure version is selectively applied only when sensitive data is being processed, ensuring optimal performance for instructions operating on non-sensitive data. To evaluate our approach, we implement it on the RISC-V out-of-order BOOM processor. Our results demonstrate that the mechanism increases FPGA resource utilization by only 2% compared to the original design. Additionally, it imposes 0% performance overhead for unprotected applications, while maintaining overhead between up to 25% for security-critical workloads. This work represents a scalable and efficient solution for defending against micro-architectural side-channel attacks without compromising system performance."]},{"key":"dc:title","label":"Title","values":["Fortifying System Security: Exploring Attacks and Desgning Robust Defenses"]}]}],"canonical_facts":{"dc:date.issued":["2025"],"dc:description.other":["Cyberattacks are the fastest-growing crime in the U.S., costing the economy billions of dollars annually. These attacks use system vulnerabilities to leak Information or steal identity through unauthorized access (AT&T 2024, Microsoft 2021, and Facebook 2019). Although researchers traditionally considered software as the origin of these threats and left hardware as a trusted party, emerging Hardware Trojans and Micro-architectural Attacks have shown that the hardware can be easily leveraged as a source of leakage to compromise the system security. Hence, this dissertation pursues two directions to mitigate hardware vulnerabilities by generating an evasive hardware Trojan and mitigating the micro-architectural attacks.In the first direction, we investigate threats that exploit hardware Trojans (HTs)- a small malicious modification in hardware causing malfunction, leakage of confidential information, or leading to other disastrous consequences- as a source of leakage. To this aim, we question the trustworthiness of ML-based HT detection via a side-channel analysis, which is a widely used approach to detecting HTs since they don’t require a golden chip (reference chips used to verify the design), are non-intrusive, and highly efficient. Therefore, this dissertation introduces an HT obfuscation (HTO) approach to allow HTs to bypass this detection method. Rather than theoretically misleading the model by simulated adversarial traces, a key aspect of our approach is the design and implementation of adversarial noise as part of the circuitry, alongside the HT. We detail HTO methodologies for ASICs and FPGAs and evaluate our approach using the TrustHub benchmark. Interestingly, we found that HTO can be implemented with only a single transistor for ASIC designs to generate adversarial power traces that can fool the defense with 100% efficiency. We also efficiently implemented our approach on a Spartan 6 Xilinx FPGA using 2 different variants: (i) DSP slices-based, and (ii) ring-oscillator-based design. Additionally, we assess the efficiency of countermeasures like spectral domain analysis and adversarial training (AT) on the proposed method. Despite restricting the spectral noise budget can impact the attack efficiency, we show that an adaptive attacker can still design evasive HTOs by constraining the design with a spectral noise budget. In addition, while adversarial training (AT) offers higher protection against evasive HTs, AT models suffer from a considerable utility loss, potentially rendering them unsuitable for such security applications. In the second direction, first, we explore transient execution attacks, such as Spectre and Meltdown, targeting speculative execution (a micro-architectural optimization in modern processors) to access privileged data and leak it through a side channel. To this aim, we present a framework that automates the finding of exploitable Spectre gadgets in a code given a black-box micro-architecture. The main goal is to precisely identify contention-based Spectre gadgets (avoid false positives to reduce the mitigation overhead). We need to focus on finding contention between transiently executed instructions and non-transient ones, which is the type of contention used in transient execution attacks to be able to leak the secret during transient execution. Therefore, the framework enables automation by viewing on-core contention between different instructions, which allows treating the tar- geted CPU micro-architecture as a black box. Specifically, the framework first generates contention maps for a targeted black-box micro-architecture, which show the level of inter- action between each pair of instructions in Instruction Set Architecture (ISA) when one is run transiently and the other runs non-transiently. Subsequently, contention maps are fed into a static code analysis tool that we designed and developed to precisely find exploitable gadgets for a given code when it runs on a given black-box micro-architecture. Second, we propose a generic approach to mitigate micro-architectural side-channel attacks with minimal architectural changes. Unlike traditional approaches that focus on mitigating specific side channels, we propose a dynamic strategy that alters the decoding of the instructions into secure (side-channel resilient) or performance versions of the instructions, based on the data it is processing. Specifically, to minimize performance overhead, decoding to a secure version is selectively applied only when sensitive data is being processed, ensuring optimal performance for instructions operating on non-sensitive data. To evaluate our approach, we implement it on the RISC-V out-of-order BOOM processor. Our results demonstrate that the mechanism increases FPGA resource utilization by only 2% compared to the original design. Additionally, it imposes 0% performance overhead for unprotected applications, while maintaining overhead between up to 25% for security-critical workloads. This work represents a scalable and efficient solution for defending against micro-architectural side-channel attacks without compromising system performance."],"dc:identifier":["hdl:1920/15207"],"dc:subject":["Adversarial Attack","Hardware Trojans","Machine Learning","Micro-architectural Side-channel Attacks","Spectre Attack"],"dc:title":["Fortifying System Security: Exploring Attacks and Desgning Robust Defenses"],"dc:type":["Dissertation"]},"updated_at":"2026-07-27T19:52:00Z"}