{"id":{"repo_id":"gatech","oai_identifier":"oai:repository.gatech.edu:1853/66554"},"canonical_url":"https://search.dev.ndltd.org/etd/gatech/oai:repository.gatech.edu:1853/66554","repository":{"repo_id":"gatech","name":"Georgia Tech","base_url":"https://repository.gatech.edu/server/oai/request"},"display":{"title":"ELECTRONIC DESIGN AUTOMATION TOOLS AND DESIGN STUDY FOR HETEROGENEOUS MONOLITHIC 3D INTEGRATED CIRCUITS","abstract":"Technology scaling predicted by Moore's law is gradually slowing down and new alternatives to silicon-based transistors are being explored. Some of the most promising solutions make use of materials such as carbon nanotubes or ferroelectric layers in the gate stack. While such materials bring improvements to the transistor performance, Three Dimensional (3D) Integrated Circuit (IC) Design, which is the focus of this work, is another promising alternative for going beyond Moore’s Law. 3D IC provides power, performance, and area (PPA) benefits at full-chip level, orthogonal to the transistor improvements by stacking multiple smaller 2D dies vertically instead of using a single large 2D die. The objective of this research is to explore and exploit novel design configurations possible with 3D ICs. Furthermore, tool flows and algorithms were developed to augment and capitalize on the commercially available 2D Electronic Design Automation (EDA) tools to support our exploration. While most of the work is done based on assumptions related to the state-of-the-art research fabrication methods for 3D such as Monolithic 3D ICs, we also develop new flows to refine the 3D IC routing with commercially available fabrication techniques such as hybrid bonding and micro-bump based 3D ICs.","abstract_html":"Technology scaling predicted by Moore's law is gradually slowing down and new alternatives to silicon-based transistors are being explored. Some of the most promising solutions make use of materials such as carbon nanotubes or ferroelectric layers in the gate stack. While such materials bring improvements to the transistor performance, Three Dimensional (3D) Integrated Circuit (IC) Design, which is the focus of this work, is another promising alternative for going beyond Moore’s Law. 3D IC provides power, performance, and area (PPA) benefits at full-chip level, orthogonal to the transistor improvements by stacking multiple smaller 2D dies vertically instead of using a single large 2D die. The objective of this research is to explore and exploit novel design configurations possible with 3D ICs. Furthermore, tool flows and algorithms were developed to augment and capitalize on the commercially available 2D Electronic Design Automation (EDA) tools to support our exploration. While most of the work is done based on assumptions related to the state-of-the-art research fabrication methods for 3D such as Monolithic 3D ICs, we also develop new flows to refine the 3D IC routing with commercially available fabrication techniques such as hybrid bonding and micro-bump based 3D ICs.","abstract_has_math":false,"creators":["Pentapati, Sai Surya Kiran"],"institution":"Georgia Institute of Technology","degree_name":null,"degree_level":"Doctoral","degree_discipline":null,"degree_department":"Electrical and Computer Engineering","school":null,"contributors":[],"advisors":["Lim, Sung Kyu"],"committee_chairs":[],"committee_members":["Yu, Shimeng","Mukhopadhyay, Saibal","Hao, Callie","Kim, Hyesoon"],"year":2022,"date_issued":"2022-04-13","date_published":"2022-04-13","updated_at":"2026-07-27T19:50:58Z","subjects":["3D Integrated Circuits","Electronic Design Automation Tools","Heterogeneous Circuits"],"languages":["en_US"],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/1853/66554","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Lim, Sung Kyu"]},{"key":"dc:contributor.committeemember","label":"Committee Member","values":["Yu, Shimeng","Mukhopadhyay, Saibal","Hao, Callie","Kim, Hyesoon"]},{"key":"dc:contributor.department","label":"Department","values":["Electrical and Computer Engineering"]},{"key":"dc:creator","label":"Author","values":["Pentapati, Sai Surya Kiran"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2022-05-18T19:32:13Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2022-05-18T19:32:13Z"]},{"key":"dc:date.issued","label":"Date","values":["2022-04-13"]},{"key":"dc:publisher","label":"Institution","values":["Georgia Institute of Technology"]},{"key":"dc:type","label":"Dc Type","values":["Text"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Doctoral"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["3D Integrated Circuits","Electronic Design Automation Tools","Heterogeneous Circuits"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en_US"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/1853/66554"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["Technology scaling predicted by Moore's law is gradually slowing down and new alternatives to silicon-based transistors are being explored. Some of the most promising solutions make use of materials such as carbon nanotubes or ferroelectric layers in the gate stack. While such materials bring improvements to the transistor performance, Three Dimensional (3D) Integrated Circuit (IC) Design, which is the focus of this work, is another promising alternative for going beyond Moore’s Law. 3D IC provides power, performance, and area (PPA) benefits at full-chip level, orthogonal to the transistor improvements by stacking multiple smaller 2D dies vertically instead of using a single large 2D die. The objective of this research is to explore and exploit novel design configurations possible with 3D ICs. Furthermore, tool flows and algorithms were developed to augment and capitalize on the commercially available 2D Electronic Design Automation (EDA) tools to support our exploration. While most of the work is done based on assumptions related to the state-of-the-art research fabrication methods for 3D such as Monolithic 3D ICs, we also develop new flows to refine the 3D IC routing with commercially available fabrication techniques such as hybrid bonding and micro-bump based 3D ICs."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["Ph.D."]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["ELECTRONIC DESIGN AUTOMATION TOOLS AND DESIGN STUDY FOR HETEROGENEOUS MONOLITHIC 3D INTEGRATED CIRCUITS"]}]}],"canonical_facts":{"dc:contributor.advisor":["Lim, Sung Kyu"],"dc:contributor.committeemember":["Yu, Shimeng","Mukhopadhyay, Saibal","Hao, Callie","Kim, Hyesoon"],"dc:contributor.department":["Electrical and Computer Engineering"],"dc:creator":["Pentapati, Sai Surya Kiran"],"dc:date.accessioned":["2022-05-18T19:32:13Z"],"dc:date.available":["2022-05-18T19:32:13Z"],"dc:date.issued":["2022-04-13"],"dc:description.abstract":["Technology scaling predicted by Moore's law is gradually slowing down and new alternatives to silicon-based transistors are being explored. Some of the most promising solutions make use of materials such as carbon nanotubes or ferroelectric layers in the gate stack. While such materials bring improvements to the transistor performance, Three Dimensional (3D) Integrated Circuit (IC) Design, which is the focus of this work, is another promising alternative for going beyond Moore’s Law. 3D IC provides power, performance, and area (PPA) benefits at full-chip level, orthogonal to the transistor improvements by stacking multiple smaller 2D dies vertically instead of using a single large 2D die. The objective of this research is to explore and exploit novel design configurations possible with 3D ICs. Furthermore, tool flows and algorithms were developed to augment and capitalize on the commercially available 2D Electronic Design Automation (EDA) tools to support our exploration. While most of the work is done based on assumptions related to the state-of-the-art research fabrication methods for 3D such as Monolithic 3D ICs, we also develop new flows to refine the 3D IC routing with commercially available fabrication techniques such as hybrid bonding and micro-bump based 3D ICs."],"dc:description.degree":["Ph.D."],"dc:format.mimetype":["application/pdf"],"dc:identifier.uri":["http://hdl.handle.net/1853/66554"],"dc:language.iso":["en_US"],"dc:publisher":["Georgia Institute of Technology"],"dc:subject":["3D Integrated Circuits","Electronic Design Automation Tools","Heterogeneous Circuits"],"dc:title":["ELECTRONIC DESIGN AUTOMATION TOOLS AND DESIGN STUDY FOR HETEROGENEOUS MONOLITHIC 3D INTEGRATED CIRCUITS"],"dc:type":["Text"],"thesis:degree_level":["Doctoral"]},"updated_at":"2026-07-27T19:50:58Z"}