{"id":{"repo_id":"gatech","oai_identifier":"oai:repository.gatech.edu:1853/64712"},"canonical_url":"https://search.dev.ndltd.org/etd/gatech/oai:repository.gatech.edu:1853/64712","repository":{"repo_id":"gatech","name":"Georgia Tech","base_url":"https://repository.gatech.edu/server/oai/request"},"display":{"title":"Design and Reliability of mm-Wave Circuits In Silicon-Germanium","abstract":"The first goal of this research is to develop a methodology for the design of RF and mm-Wave circuits in Silicon-Germanium utilizing CMOS, PIN diodes, and passive circuits. Such circuits consist of a 2-20 GHz CMOS-based TR (Transmit/Receive) SPDT switch and an 18-47 GHz Wilkinson Power Divider-Combiner (WPDC). Optimal design techniques are utilized in these circuit designs to overcome the limitations of both Front End of the Line (FEOL: active devices) and Back End of the Line (BEOL: metal stack-up) in a commercial SiGe BiCMOS processes. The resulting performances utilize novel design techniques that allow them to be competitive with existing state-of-the-art designs across multiple IC technologies. The second goal of this research is to understand the impact of DC reliability mechanisms on AC performance for analog SiGe HBT circuits and to locate an optimal DC biasing regime that balances the tradeoff between circuit reliability and performance. The circuit of interest is a DC-100 GHz wireline driver, which is widely used as a critical block in optical communications. The aim is to extend the concept of Safe Operating Area (SOA), which is the region of the DC I-V plane that does not damage a device over time, to the circuit level. This is done with the introduction of a performance-informed Circuit Safe Operating Area (C-SOA), which is defined as the region of the DC I-V plane that does not result in a degradation to AC performance over time while maintaining the best possible AC performance. The wireline driver's highlighted AC performance is the OP1dB or output referred 1-dB compression point.","abstract_html":"The first goal of this research is to develop a methodology for the design of RF and mm-Wave circuits in Silicon-Germanium utilizing CMOS, PIN diodes, and passive circuits. Such circuits consist of a 2-20 GHz CMOS-based TR (Transmit/Receive) SPDT switch and an 18-47 GHz Wilkinson Power Divider-Combiner (WPDC). Optimal design techniques are utilized in these circuit designs to overcome the limitations of both Front End of the Line (FEOL: active devices) and Back End of the Line (BEOL: metal stack-up) in a commercial SiGe BiCMOS processes. The resulting performances utilize novel design techniques that allow them to be competitive with existing state-of-the-art designs across multiple IC technologies. The second goal of this research is to understand the impact of DC reliability mechanisms on AC performance for analog SiGe HBT circuits and to locate an optimal DC biasing regime that balances the tradeoff between circuit reliability and performance. The circuit of interest is a DC-100 GHz wireline driver, which is widely used as a critical block in optical communications. The aim is to extend the concept of Safe Operating Area (SOA), which is the region of the DC I-V plane that does not damage a device over time, to the circuit level. This is done with the introduction of a performance-informed Circuit Safe Operating Area (C-SOA), which is defined as the region of the DC I-V plane that does not result in a degradation to AC performance over time while maintaining the best possible AC performance. The wireline driver's highlighted AC performance is the OP1dB or output referred 1-dB compression point.","abstract_has_math":false,"creators":["Moradinia, Arya"],"institution":"Georgia Institute of Technology","degree_name":null,"degree_level":"Masters","degree_discipline":null,"degree_department":"Electrical and Computer Engineering","school":null,"contributors":[],"advisors":["Cressler, John D."],"committee_chairs":[],"committee_members":["Scott, Waymond","Li, Shaolan"],"year":2021,"date_issued":"2021-05-04","date_published":"2021-05-04","updated_at":"2026-07-27T19:49:34Z","subjects":["SiGe","Circuit Design","Reliability"],"languages":["en_US"],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/1853/64712","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Cressler, John D."]},{"key":"dc:contributor.committeemember","label":"Committee Member","values":["Scott, Waymond","Li, Shaolan"]},{"key":"dc:contributor.department","label":"Department","values":["Electrical and Computer Engineering"]},{"key":"dc:creator","label":"Author","values":["Moradinia, Arya"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2021-06-10T16:51:19Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2021-06-10T16:51:19Z"]},{"key":"dc:date.issued","label":"Date","values":["2021-05-04"]},{"key":"dc:publisher","label":"Institution","values":["Georgia Institute of Technology"]},{"key":"dc:type","label":"Dc Type","values":["Text"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Masters"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["SiGe","Circuit Design","Reliability"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en_US"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/1853/64712"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["The first goal of this research is to develop a methodology for the design of RF and mm-Wave circuits in Silicon-Germanium utilizing CMOS, PIN diodes, and passive circuits. Such circuits consist of a 2-20 GHz CMOS-based TR (Transmit/Receive) SPDT switch and an 18-47 GHz Wilkinson Power Divider-Combiner (WPDC). Optimal design techniques are utilized in these circuit designs to overcome the limitations of both Front End of the Line (FEOL: active devices) and Back End of the Line (BEOL: metal stack-up) in a commercial SiGe BiCMOS processes. The resulting performances utilize novel design techniques that allow them to be competitive with existing state-of-the-art designs across multiple IC technologies. The second goal of this research is to understand the impact of DC reliability mechanisms on AC performance for analog SiGe HBT circuits and to locate an optimal DC biasing regime that balances the tradeoff between circuit reliability and performance. The circuit of interest is a DC-100 GHz wireline driver, which is widely used as a critical block in optical communications. The aim is to extend the concept of Safe Operating Area (SOA), which is the region of the DC I-V plane that does not damage a device over time, to the circuit level. This is done with the introduction of a performance-informed Circuit Safe Operating Area (C-SOA), which is defined as the region of the DC I-V plane that does not result in a degradation to AC performance over time while maintaining the best possible AC performance. The wireline driver's highlighted AC performance is the OP1dB or output referred 1-dB compression point."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["M.S."]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Design and Reliability of mm-Wave Circuits In Silicon-Germanium"]}]}],"canonical_facts":{"dc:contributor.advisor":["Cressler, John D."],"dc:contributor.committeemember":["Scott, Waymond","Li, Shaolan"],"dc:contributor.department":["Electrical and Computer Engineering"],"dc:creator":["Moradinia, Arya"],"dc:date.accessioned":["2021-06-10T16:51:19Z"],"dc:date.available":["2021-06-10T16:51:19Z"],"dc:date.issued":["2021-05-04"],"dc:description.abstract":["The first goal of this research is to develop a methodology for the design of RF and mm-Wave circuits in Silicon-Germanium utilizing CMOS, PIN diodes, and passive circuits. Such circuits consist of a 2-20 GHz CMOS-based TR (Transmit/Receive) SPDT switch and an 18-47 GHz Wilkinson Power Divider-Combiner (WPDC). Optimal design techniques are utilized in these circuit designs to overcome the limitations of both Front End of the Line (FEOL: active devices) and Back End of the Line (BEOL: metal stack-up) in a commercial SiGe BiCMOS processes. The resulting performances utilize novel design techniques that allow them to be competitive with existing state-of-the-art designs across multiple IC technologies. The second goal of this research is to understand the impact of DC reliability mechanisms on AC performance for analog SiGe HBT circuits and to locate an optimal DC biasing regime that balances the tradeoff between circuit reliability and performance. The circuit of interest is a DC-100 GHz wireline driver, which is widely used as a critical block in optical communications. The aim is to extend the concept of Safe Operating Area (SOA), which is the region of the DC I-V plane that does not damage a device over time, to the circuit level. This is done with the introduction of a performance-informed Circuit Safe Operating Area (C-SOA), which is defined as the region of the DC I-V plane that does not result in a degradation to AC performance over time while maintaining the best possible AC performance. The wireline driver's highlighted AC performance is the OP1dB or output referred 1-dB compression point."],"dc:description.degree":["M.S."],"dc:format.mimetype":["application/pdf"],"dc:identifier.uri":["http://hdl.handle.net/1853/64712"],"dc:language.iso":["en_US"],"dc:publisher":["Georgia Institute of Technology"],"dc:subject":["SiGe","Circuit Design","Reliability"],"dc:title":["Design and Reliability of mm-Wave Circuits In Silicon-Germanium"],"dc:type":["Text"],"thesis:degree_level":["Masters"]},"updated_at":"2026-07-27T19:49:34Z"}