Process modeling and optimization using industrial semiconductor fabrication data

Manufacturers address the distinct operational objectives of product innovation and manufacturing efficiency by having separate fabrication facilities (“fabs”) for development and manufacturing. Additionally, the industrial manufacture of a semiconductor product proceeds through several stages of production. These are typically a research and development (R&D) stage, a ramping stage, and a manufacturing stage. These production stages are distributed over the different fabs. These differences in fabrication environment and stage of production result in differences in the characteristics of production of a semiconductor product over its manufacturing lifetime. Some examples of these differences are device yield, breadth of processing conditions, throughput, number of reaction chambers operating in parallel, metrology, and data collection. These differences are reflected in the data available in the fab databases. This research explores the use of a neural network modeling and genetic algorithm optimization method with these different datasets. The focus is on a high-aspect-ratio etch process across the different fabs and production stages. Models are built from process input variables to post-process metrology, and from process input variables to yield metrics. In the latter case, there can be tens of processes occurring between the model input and output variables. I demonstrate the usefulness and industrial application of neural network process modeling and genetic algorithm recipe optimization by performing a reaction chamber matching exercise on a manufacturing line. The performance of a reaction chamber can deviate from target, either in terms of its post-process metrology or its associated yield metrics. The method developed herein generated an optimized recipe that brought the outlying behavior of a chamber closer to target and closer to that of the other chambers (“chamber matching”). This is one of many possible applications. It was chosen because it demonstrates both the fidelity of the process models and the effectiveness of the optimization algorithm.

Level thesis:degree_level

Doctoral

Department dc:contributor.department

Electrical and Computer Engineering

Grantor dc:publisher

Georgia Institute of Technology

Year dc:date.issued

2015

Author dc:creator

• Mevawalla, Zubin

Advisor dc:contributor.advisor

• May, Gary S.

Committee members dc:contributor.committeemember

• Frazier, Albert B.
• Milor, Linda S.
• Bakir, Muhannad S.
• Kohl, Paul A.

• Semiconductor manufacturing
• Neural networks
• Machine learning
• Process modeling
• Process control
• Chamber matching

Handle dc:identifier.uri

http://hdl.handle.net/1853/53382

OAI identifier oai:identifier

oai:repository.gatech.edu:1853/53382