Frequency dividers design for multi-GHz PLL systems

In this work, a programmable frequency divider suitable for millimeter wave phase-lock loops is presented. The frequency divider has been implemented in a 90 nm standard CMOS technology. To the extent of maximizing the operative input frequency, the higher frequency digital blocks of the frequency divider have been realized using dynamic precharge-evaluation logic. Moreover, a non-conventional method to implement non-power-of-2 division ratios has been used for the higher frequency divider stages (input stages).

Department dc:contributor.department

Electrical and Computer Engineering

Grantor dc:publisher

Georgia Institute of Technology

Year dc:date.issued

2008

Author dc:creator

• Barale, Francesco

Advisor dc:contributor.advisor

• Laskar, Joy

Committee members dc:contributor.committeemember

• Cressler, John D.
• Tentzeris Emmanouil

• CMOS integrated circuits
• Frequency dividers

Handle dc:identifier.uri

http://hdl.handle.net/1853/24610

OAI identifier oai:identifier

oai:repository.gatech.edu:1853/24610